From: Rik van Riel <riel@surriel.com>
To: Michal Hocko <mhocko@suse.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
lsf-pc@lists.linux-foundation.org, linux-mm@kvack.org
Subject: LSFMMBPF - topic - TLB flush, TLB miss rate, and related things
Date: Wed, 19 Mar 2025 13:10:31 -0400 [thread overview]
Message-ID: <97e5bb8451c99bc1aad5e3d9ce56a7a2e39cb009.camel@surriel.com> (raw)
In-Reply-To: <Z9mcRcqJlJU_Qjde@tiehlicka>
A few things related to TLB flushing and TLB miss rates
I would like to discuss at LSF/MM:
1) A quick update on IPI-less TLB flushing with
AMD INVLPGB and Intel RAR, and implications
for MM synchronization. Probably no real
discussion needed.
2) A discussion on how we might be able to
integrate mTHPs into khugepaged, and get
TLB miss benefits on AMD and ARM CPUs for
processes where full-size THPs cause too
much memory waste due to internal fragmentation.
Are there any other related topics we should try to
fit into the same time slot?
--
All Rights Reversed.
parent reply other threads:[~2025-03-19 17:15 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <Z9mcRcqJlJU_Qjde@tiehlicka>]
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