From: Alexandre Ghiti <alex@ghiti.fr>
To: Pedro Falcato <pedro.falcato@gmail.com>,
Kees Cook <keescook@chromium.org>
Cc: Conor Dooley <conor@kernel.org>,
Sami Tolvanen <samitolvanen@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Morton <akpm@linux-foundation.org>,
linux-mm@kvack.org, linux-riscv@lists.infradead.org,
llvm@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] riscv: mm: Update mmap_rnd_bits_max
Date: Mon, 2 Oct 2023 09:02:42 +0200 [thread overview]
Message-ID: <8d305ae1-4235-6ae8-7dfb-9f432fdfcd41@ghiti.fr> (raw)
In-Reply-To: <CAKbZUD08W9_HB9F7tQqwreYvVapgVMOkS3QokzwHPcBnFnVMig@mail.gmail.com>
On 01/10/2023 17:19, Pedro Falcato wrote:
> On Sun, Oct 1, 2023 at 2:51 AM Kees Cook <keescook@chromium.org> wrote:
>> On Sat, Sep 30, 2023 at 10:02:35AM +0100, Conor Dooley wrote:
>>> On Fri, Sep 29, 2023 at 03:52:22PM -0700, Sami Tolvanen wrote:
>>>> On Fri, Sep 29, 2023 at 2:54 PM Kees Cook <keescook@chromium.org> wrote:
>>>>> On Fri, Sep 29, 2023 at 09:11:58PM +0000, Sami Tolvanen wrote:
>>>>>> ARCH_MMAP_RND_BITS_MAX is based on Sv39, which leaves a few
>>>>>> potential bits of mmap randomness on the table if we end up enabling
>>>>>> 4/5-level paging. Update mmap_rnd_bits_max to take the final address
>>>>>> space size into account. This increases mmap_rnd_bits_max from 24 to
>>>>>> 33 with Sv48/57.
>>>>>>
>>>>>> Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
>>>>> I like this. Is RISCV the only arch where the paging level can be chosen
>>>>> at boot time?
>>>> I haven't seen this elsewhere, but I also haven't looked at all the
>>>> other architectures that closely. arm64 does something interesting
>>>> with ARM64_VA_BITS_52, but I think we can still handle that in
>>>> Kconfig.
>>> AFAIU, x86-64 can do this also:
>>>
>>> no4lvl [RISCV] Disable 4-level and 5-level paging modes. Forces
>>> kernel to use 3-level paging instead.
>>>
>>> no5lvl [X86-64,RISCV] Disable 5-level paging mode. Forces
>>> kernel to use 4-level paging instead.
>> Ah-ha! Okay, well, then let's track this idea:
>> https://github.com/KSPP/linux/issues/346
> (Replying here for visibility, tell me if you want to move this
> discussion to github)
>
> AIUI, x86 cannot do this for compat reasons. Even if you enable LA57,
> mmap only gives you < 48-bit addresses, for compatibility with things
> like JITs, etc that stash information in the upper 16 bits. You need
> to pass a > 48-bit mmap hint to get 57-bit addresses.
>
> I imagine riscv does not have this issue yet, due to little
> accumulated cruft, but it may be wise to check against popular JITters
> for these problems on riscv code.
>
We already encountered those issues and the same solution was recently
merged (restrict to sv48 unless otherwise specified):
https://lore.kernel.org/all/20230809232218.849726-1-charlie@rivosinc.com/
next prev parent reply other threads:[~2023-10-02 7:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-29 21:11 [PATCH 0/2] riscv: Increase mmap_rnd_bits_max on Sv48/57 Sami Tolvanen
2023-09-29 21:11 ` [PATCH 1/2] mm: Change mmap_rnd_bits_max to __ro_after_init Sami Tolvanen
2023-09-29 21:55 ` Kees Cook
2023-09-29 21:11 ` [PATCH 2/2] riscv: mm: Update mmap_rnd_bits_max Sami Tolvanen
2023-09-29 21:54 ` Kees Cook
2023-09-29 22:52 ` Sami Tolvanen
2023-09-30 9:02 ` Conor Dooley
2023-09-30 21:01 ` Kees Cook
2023-10-01 15:19 ` Pedro Falcato
2023-10-02 7:02 ` Alexandre Ghiti [this message]
2023-10-02 15:58 ` Sami Tolvanen
2023-12-06 13:14 ` [PATCH 0/2] riscv: Increase mmap_rnd_bits_max on Sv48/57 Palmer Dabbelt
2023-12-06 20:28 ` Kees Cook
2024-01-17 20:29 ` Sami Tolvanen
2024-01-25 21:30 ` patchwork-bot+linux-riscv
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