From: Zhenyu Ye <yezhenyu2@huawei.com>
To: Marc Zyngier <maz@kernel.org>
Cc: <will@kernel.org>, <mark.rutland@arm.com>,
<catalin.marinas@arm.com>, <aneesh.kumar@linux.ibm.com>,
<akpm@linux-foundation.org>, <npiggin@gmail.com>,
<peterz@infradead.org>, <arnd@arndb.de>, <rostedt@goodmis.org>,
<suzuki.poulose@arm.com>, <tglx@linutronix.de>,
<yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>
Subject: Re: [RFC PATCH v4 3/6] arm64: Add level-hinted TLB invalidation helper to tlbi_user
Date: Wed, 25 Mar 2020 10:47:31 +0800 [thread overview]
Message-ID: <8cf6c576-f0e2-9a52-6919-cb5e27d2ffb5@huawei.com> (raw)
In-Reply-To: <20200324141939.51917225@why>
Hi Marc,
On 2020/3/24 22:19, Marc Zyngier wrote:
> On Tue, 24 Mar 2020 21:45:31 +0800
> Zhenyu Ye <yezhenyu2@huawei.com> wrote:
>
>> Add a level-hinted parameter to __tlbi_user, which only gets used
>> if ARMv8.4-TTL gets detected.
>>
>> ARMv8.4-TTL provides the TTL field in tlbi instruction to indicate
>> the level of translation table walk holding the leaf entry for the
>> address that is being invalidated.
>>
>> This patch set the default level value to 0.
>>
>> Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
>> ---
>> arch/arm64/include/asm/tlbflush.h | 42 ++++++++++++++++++++++++++-----
>> 1 file changed, 36 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
>> index a3f70778a325..d141c080e494 100644
>> --- a/arch/arm64/include/asm/tlbflush.h
>> +++ b/arch/arm64/include/asm/tlbflush.h
>> @@ -89,6 +89,36 @@
>> __tlbi(op, arg); \
>> } while(0)
>>
>> +#define __tlbi_user_level(op, addr, level) \
>> + do { \
>> + u64 arg = addr; \
>> + \
>> + if (!arm64_kernel_unmapped_at_el0()) \
>> + break; \
>> + \
>> + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
>> + level) { \
>> + u64 ttl = level; \
>> + \
>> + switch (PAGE_SIZE) { \
>> + case SZ_4K: \
>> + ttl |= 1 << 2; \
>> + break; \
>> + case SZ_16K: \
>> + ttl |= 2 << 2; \
>> + break; \
>> + case SZ_64K: \
>> + ttl |= 3 << 2; \
>> + break; \
>> + } \
>> + \
>> + arg &= ~TLBI_TTL_MASK; \
>> + arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
>> + } \
>> + \
>> + __tlbi(op, (arg) | USER_ASID_FLAG);
>> \
>> + } while (0)
>> +
>
> Isn't this just:
>
> define __tlbi_user_level(op, addr, level) \
> do { \
> if (!arm64_kernel_unmapped_at_el0()) \
> break; \
> \
> __tlbi_level(op, addr | USER_ASID_FLAG, level); \
> } while (0)
>
> Thanks,
>
> M.
>
Yeah, your code is more clear! I will take it in next version. ;-)
Thanks,
zhenyu
next prev parent reply other threads:[~2020-03-25 2:48 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 13:45 [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 3/6] arm64: Add level-hinted TLB invalidation helper to tlbi_user Zhenyu Ye
2020-03-24 14:19 ` Marc Zyngier
2020-03-25 2:47 ` Zhenyu Ye [this message]
2020-03-24 13:45 ` [RFC PATCH v4 4/6] mm: Add page table level flags to vm_flags Zhenyu Ye
2020-03-24 18:44 ` Steven Rostedt
2020-03-25 2:10 ` yezhenyu (A)
2020-03-24 13:45 ` [RFC PATCH v4 5/6] arm64: tlb: Use translation level hint in vm_flags Zhenyu Ye
2020-03-24 14:45 ` Marc Zyngier
2020-03-25 8:00 ` Zhenyu Ye
2020-03-25 14:13 ` Marc Zyngier
2020-03-26 7:11 ` Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 6/6] mm: Set VM_LEVEL flags in some tlb_flush functions Zhenyu Ye
2020-03-24 15:01 ` [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature Peter Zijlstra
2020-03-25 4:49 ` Zhenyu Ye
2020-03-25 13:32 ` Peter Zijlstra
2020-03-26 7:15 ` Zhenyu Ye
2020-03-25 16:15 ` James Morse
2020-03-25 16:41 ` Peter Zijlstra
2020-03-26 6:45 ` Zhenyu Ye
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