From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89F08C07E95 for ; Fri, 16 Jul 2021 07:05:34 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 2C2AA613C0 for ; Fri, 16 Jul 2021 07:05:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2C2AA613C0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 55E208D00F4; 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Fri, 16 Jul 2021 00:05:31 -0700 (PDT) Received: from [10.163.67.71] (unknown [10.163.67.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 350B63F7D8; Fri, 16 Jul 2021 00:05:27 -0700 (PDT) Subject: Re: [RFC 07/10] arm64/mm: Detect and enable FEAT_LPA2 To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: akpm@linux-foundation.org, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com, steven.price@arm.com References: <1626229291-6569-1-git-send-email-anshuman.khandual@arm.com> <1626229291-6569-8-git-send-email-anshuman.khandual@arm.com> <18c42dd0-b6db-d118-dad0-cac0bf6ab2ce@arm.com> From: Anshuman Khandual Message-ID: <8adefac5-c677-1fca-20dd-bba8543f8d59@arm.com> Date: Fri, 16 Jul 2021 12:36:15 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <18c42dd0-b6db-d118-dad0-cac0bf6ab2ce@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Authentication-Results: imf03.hostedemail.com; dkim=none; spf=pass (imf03.hostedemail.com: domain of anshuman.khandual@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=anshuman.khandual@arm.com; dmarc=pass (policy=none) header.from=arm.com X-Stat-Signature: 15gku7wbnbid1u6dijghmz7sarhj1wju X-Rspamd-Queue-Id: 271CB30001B8 X-Rspamd-Server: rspam01 X-HE-Tag: 1626419132-915824 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 7/14/21 1:51 PM, Suzuki K Poulose wrote: > On 14/07/2021 03:21, Anshuman Khandual wrote: >> Detect FEAT_LPA2 implementation early enough during boot when requeste= d via >> CONFIG_ARM64_PA_BITS_52_LPA2 and remember in a variable arm64_lpa2_ena= bled. >> This variable could then be used to turn on TCR_EL1.TCR_DS effecting t= he 52 >> bits PA range or fall back to default 48 bits PA range if FEAT_LPA2 fe= ature >> was requested but found not to be implemented. >> >> Signed-off-by: Anshuman Khandual >> --- >> =C2=A0 arch/arm64/include/asm/memory.h |=C2=A0 1 + >> =C2=A0 arch/arm64/kernel/head.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 | 15 +++++++++++++++ >> =C2=A0 arch/arm64/mm/mmu.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 3 +++ >> =C2=A0 arch/arm64/mm/proc.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0 9 +++++++++ >> =C2=A0 4 files changed, 28 insertions(+) >> >> diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/= memory.h >> index 824a365..d0ca002 100644 >> --- a/arch/arm64/include/asm/memory.h >> +++ b/arch/arm64/include/asm/memory.h >> @@ -178,6 +178,7 @@ >> =C2=A0 #include >> =C2=A0 =C2=A0 extern u64=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 vabits_actual; >> +extern u64=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 arm64_lpa2_enabled; >> =C2=A0 =C2=A0 extern s64=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 memstart_addr; >> =C2=A0 /* PHYS_OFFSET - the physical address of the start of memory. *= / >> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S >> index 6444147..9cf79ea 100644 >> --- a/arch/arm64/kernel/head.S >> +++ b/arch/arm64/kernel/head.S >> @@ -94,6 +94,21 @@ SYM_CODE_START(primary_entry) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 adrp=C2=A0=C2=A0=C2=A0 x23, __PHYS_OFFS= ET >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 and=C2=A0=C2=A0=C2=A0 x23, x23, MIN_KIM= G_ALIGN - 1=C2=A0=C2=A0=C2=A0 // KASLR offset, defaults to 0 >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bl=C2=A0=C2=A0=C2=A0 set_cpu_boot_mode_= flag >> + >> +#ifdef CONFIG_ARM64_PA_BITS_52_LPA2 >> +=C2=A0=C2=A0=C2=A0 mrs=C2=A0=C2=A0=C2=A0=C2=A0 x10, ID_AA64MMFR0_EL1 >> +=C2=A0=C2=A0=C2=A0 ubfx=C2=A0=C2=A0=C2=A0 x10, x10, #ID_AA64MMFR0_TGR= AN_SHIFT, 4 >> +=C2=A0=C2=A0=C2=A0 cmp=C2=A0=C2=A0=C2=A0=C2=A0 x10, #ID_AA64MMFR0_TGR= AN_LPA2 >> +=C2=A0=C2=A0=C2=A0 b.ne=C2=A0=C2=A0=C2=A0 1f >=20 > For the sake of forward compatibility, this should be "b.lt" Right, I guess we could assume that the feature will be present from the current ID_AA64MMFR0_TGRAN_LPA2 values onward in the future. But should not this also be capped at ID_AA64MMFR0_TGRAN_SUPPORTED_MAX as the upper limit is different for 4K and 16K page sizes.