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Wed, 12 Nov 2025 04:57:29 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3826.700.81\)) Subject: Re: [PATCH v3] io: add io_pgtable abstraction From: Daniel Almeida In-Reply-To: <20251112-io-pgtable-v3-1-b00c2e6b951a@google.com> Date: Wed, 12 Nov 2025 09:57:09 -0300 Cc: Miguel Ojeda , Will Deacon , Boris Brezillon , Boqun Feng , Gary Guo , =?utf-8?Q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Danilo Krummrich , Joerg Roedel , Robin Murphy , Lorenzo Stoakes , "Liam R. Howlett" , Asahi Lina , linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, iommu@lists.linux.dev, linux-mm@kvack.org Content-Transfer-Encoding: quoted-printable Message-Id: <8A5C6836-992B-477A-A77C-EE0736166552@collabora.com> References: <20251112-io-pgtable-v3-1-b00c2e6b951a@google.com> To: Alice Ryhl X-Mailer: Apple Mail (2.3826.700.81) X-ZohoMailClient: External X-Stat-Signature: hj6nbd539mc4bdezo9phrym51id48drx X-Rspam-User: X-Rspamd-Queue-Id: AB9E2A0012 X-Rspamd-Server: rspam10 X-HE-Tag: 1762952255-363415 X-HE-Meta: U2FsdGVkX19qpCQ6F3CnLBrZLpL/dJmBluLsnpUf1lW3/7/ngP1sCOlYqCASkiU6HnsPAsNjgSSdmoAawBXjA5wsjSGwpq765bkn/XFMEUHSZhpYRWGTtgwyW8B/ZEgfNBJwDHlrl2b+LAPnsxrzKuc/hFvTxQ7tTRkpi6cEkCvkCFKvNEWlewOx07nwgLsbTRdrOmhD7W34VLFiGULLBl8MOv+d0CSPwK/8SBkFLWoy6f49BePL+/hSOGUvk5k/tsQS15RYaLPMBS3clOPG3vrIJpyH/kssadONue7mB+tMLMY/aJAI2nkjvWZxEsFqzN9BNpEZOvtwCCDZkIg2NZop5BeLXBtJVJeb6TaNaegKMdchGOwAa5s0g4KK4ja54OOw+2FcIBqQoH6gZwj/oxAtNfwuEX17KtkFd756e7WgGTLlMqaXkAgDdf2ZomFWQMx+UDRSvwIGHRJ61NozhtrrAkMVo14cigyxGQbfKwx5QFvgN10KIHgQfb63k2nI4pr5x6PdtPGWH39vWgnw58Q9SiEcdjHqA225w+RGQIAdp16ZoY3q8pkT6abUgak3uQAKIB+CdnG/qxi517r4+5tY8ihK1EC0XLChRBKqgpGe2CYL61AWRAfIfZLiNiPiVO97f8s8i65IgDZkvjTz+2emNypraYnUStbQxHf95ehbbP5xE3dsPd64rvzusCtJz41DhIF1DNdCGszCdu8bu2ImPTXdYye0W1QL2siAJUHUAlf323vwa15voyzlyACP1V31/BkxvZ9WXYayACKXhgZpWVGde6TPQxnfF9giMxWd40s/O2yeC5uECUajsG8H/xGCjqMMil7+avxQflvrKqWbrO/BMga3xO6mNXgwMtzrXRr9XqTbmE4REbzP2FJTqd/o8j5/vYl9VcUrCgummuHbCPjK3ygZSmSV+bOU80xngvg3gm6vJUeoYLIDOVSidQsuzStFDF7qGVIQ6Bp Lxbdg/jU S+1KDjwwmgmg0Jyks7qsgpb1c2maVBli6As9PEdB4jZMV8lDmjqutbRh4/uNUhYSdPMPXiW4jlePCuLUIwKbFHwbcX50d1MA2vbpDJGHlVL1WooHFJE6koG1JC+3C5SWr+uHEmehKPiNuZMZ/ygs9yOJzE96UzJjtJeVFNEGb0d0bqcpYxwhtEhq5WufCJHZUwyQCEnUYMSkrCOtw6GO+IK/D+djX4JZ/LK0G0sL3GNNczj7o4ehAFFzQbSTvcFCia21XN1uXxzn3I16NA7Cy/e/ar3hLqyFurp9tyrEcKdqbt3gEqtXodW5WJP3m3WKU6FruwJFhE17kx/dPKd9YLpv9nb4JUBYasEWDB+OX090raeo++ZUIl1abLFI8YUu2OvzinVItrANQXchXVSw1zYqCeGZzyjnhXXjO7Ik8L1gsHSN2RbPqxZwcQ6ik+sr9dIe2gxEsaZILwF/ylRrdi3w0RPN3WY1VEo5aixeNIeuAdhtoMrzQi5kJGzAuEUbJJcJIXKdqLJkeOWzP2XdsaO4Y2lNfUFQRYhY9a/NEaoyTiFfwma80yKCQ6EioEaFTGqA4O5sA8FIrS6gd+QtAMH446vRc91kvx5RQyGrzSU9wdR54r6gfFuPscw15CIj7mAtr X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Alice, > On 12 Nov 2025, at 07:15, Alice Ryhl wrote: >=20 > From: Asahi Lina >=20 > This will be used by the Tyr driver to create and modify the page = table > of each address space on the GPU. Each time a mapping gets created or > removed by userspace, Tyr will call into GPUVM, which will figure out > which calls to map_pages and unmap_pages are required to map the data = in > question in the page table so that the GPU may access those pages when > using that address space. >=20 > The Rust type wraps the struct using a raw pointer rather than the = usual > Opaque+ARef approach because Opaque+ARef requires the target type to = be > refcounted. >=20 > Signed-off-by: Asahi Lina > Co-Developed-by: Alice Ryhl > Signed-off-by: Alice Ryhl > --- > This patch is based on [1] but I have rewritten and simplified large > parts of it. The Asahi driver no longer uses the io-pgtable = abstraction, > and Nova never planned to (since NVIDIA has its own separate memory). > Therefore, I have simplified these abstractions to fit the needs of = the > Tyr GPU driver. >=20 > This series depends on the PhysAddr typedef [2]. >=20 > [1]: = https://lore.kernel.org/all/20250623-io_pgtable-v2-1-fd72daac75f1@collabor= a.com/ > [2]: = https://lore.kernel.org/all/20251112-resource-phys-typedefs-v2-0-538307384= f82@google.com/ > --- > rust/bindings/bindings_helper.h | 3 +- > rust/kernel/io.rs | 1 + > rust/kernel/io/pgtable.rs | 254 = ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 257 insertions(+), 1 deletion(-) >=20 > diff --git a/rust/bindings/bindings_helper.h = b/rust/bindings/bindings_helper.h > index = 2e43c66635a2c9f31bd99b9817bd2d6ab89fbcf2..faab6bc9463321c092a8bbcb6281175e= 490caccd 100644 > --- a/rust/bindings/bindings_helper.h > +++ b/rust/bindings/bindings_helper.h > @@ -56,8 +56,9 @@ > #include > #include > #include > -#include > #include > +#include > +#include > #include > #include > #include > diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs > index = 56a435eb14e3a1ce72dd58b88cbf296041f1703e..5913e240d5a9814ceed52c6dc1a798e6= 4158d567 100644 > --- a/rust/kernel/io.rs > +++ b/rust/kernel/io.rs > @@ -8,6 +8,7 @@ > use crate::{bindings, build_assert, ffi::c_void}; >=20 > pub mod mem; > +pub mod pgtable; > pub mod poll; > pub mod resource; >=20 > diff --git a/rust/kernel/io/pgtable.rs b/rust/kernel/io/pgtable.rs > new file mode 100644 > index = 0000000000000000000000000000000000000000..fe05bc1673f9a7741a887a3c9bbad866= dd17a2b5 > --- /dev/null > +++ b/rust/kernel/io/pgtable.rs > @@ -0,0 +1,254 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +//! IOMMU page table management. > +//! > +//! C header: [`include/io-pgtable.h`](srctree/include/io-pgtable.h) > + > +use core::{ > + marker::PhantomData, > + ptr::NonNull, // > +}; > + > +use crate::{ > + alloc, > + bindings, > + device::{Bound, Device}, > + devres::Devres, > + error::to_result, > + io::PhysAddr, > + prelude::*, // > +}; > + > +use bindings::io_pgtable_fmt; > + > +/// Protection flags used with IOMMU mappings. > +pub mod prot { > + /// Read access. > + pub const READ: u32 =3D bindings::IOMMU_READ; > + /// Write access. > + pub const WRITE: u32 =3D bindings::IOMMU_WRITE; > + /// Request cache coherency. > + pub const CACHE: u32 =3D bindings::IOMMU_CACHE; > + /// Request no-execute permission. > + pub const NOEXEC: u32 =3D bindings::IOMMU_NOEXEC; > + /// MMIO peripheral mapping. > + pub const MMIO: u32 =3D bindings::IOMMU_MMIO; > + /// Privileged mapping. > + pub const PRIV: u32 =3D bindings::IOMMU_PRIV; > +} > + > +/// Represents a requested `io_pgtable` configuration. > +pub struct Config { > + /// Quirk bitmask (type-specific). > + pub quirks: usize, > + /// Valid page sizes, as a bitmask of powers of two. > + pub pgsize_bitmap: usize, > + /// Input address space size in bits. > + pub ias: u32, > + /// Output address space size in bits. > + pub oas: u32, > + /// IOMMU uses coherent accesses for page table walks. > + pub coherent_walk: bool, > +} > + > +/// An io page table using a specific format. > +/// > +/// # Invariants > +/// > +/// The pointer references a valid io page table. > +pub struct IoPageTable { > + ptr: NonNull, > + _marker: PhantomData, > +} > + > +// SAFETY: `struct io_pgtable_ops` is not restricted to a single = thread. > +unsafe impl Send for IoPageTable {} > +// SAFETY: `struct io_pgtable_ops` may be accessed concurrently. > +unsafe impl Sync for IoPageTable {} > + > +/// The format used by this page table. > +pub trait IoPageTableFmt: 'static { > + /// The value representing this format. > + const FORMAT: io_pgtable_fmt; > +} > + > +impl IoPageTable { > + /// Create a new `IoPageTable` as a device resource. > + #[inline] > + pub fn new( > + dev: &Device, > + config: Config, > + ) -> impl PinInit>, Error> + '_ { > + // SAFETY: Devres ensures that the value is dropped during = device unbind. > + Devres::new(dev, unsafe { Self::new_raw(dev, config) }) > + } > + > + /// Create a new `IoPageTable`. > + /// > + /// # Safety > + /// > + /// If successful, then the returned value must be dropped before = the device is unbound. > + #[inline] > + pub unsafe fn new_raw(dev: &Device, config: Config) -> = Result> { > + let mut raw_cfg =3D bindings::io_pgtable_cfg { > + quirks: config.quirks, > + pgsize_bitmap: config.pgsize_bitmap, > + ias: config.ias, > + oas: config.oas, > + coherent_walk: config.coherent_walk, > + tlb: &raw const NOOP_FLUSH_OPS, > + iommu_dev: dev.as_raw(), > + // SAFETY: All zeroes is a valid value for `struct = io_pgtable_cfg`. > + ..unsafe { core::mem::zeroed() } > + }; > + > + // SAFETY: > + // * The raw_cfg pointer is valid for the duration of this = call. > + // * The provided `FLUSH_OPS` contains valid function = pointers that accept a null pointer > + // as cookie. > + // * The caller ensures that the io pgtable does not outlive = the device. > + let ops =3D unsafe { > + bindings::alloc_io_pgtable_ops(F::FORMAT, &mut raw_cfg, = core::ptr::null_mut()) > + }; > + // INVARIANT: We successfully created a valid page table. > + Ok(IoPageTable { > + ptr: NonNull::new(ops).ok_or(ENOMEM)?, > + _marker: PhantomData, > + }) > + } > + > + /// Obtain a raw pointer to the underlying `struct = io_pgtable_ops`. > + #[inline] > + pub fn raw_ops(&self) -> *mut bindings::io_pgtable_ops { > + self.ptr.as_ptr() > + } > + > + /// Obtain a raw pointer to the underlying `struct io_pgtable`. > + #[inline] > + pub fn raw_pgtable(&self) -> *mut bindings::io_pgtable { > + // SAFETY: The io_pgtable_ops of an io-pgtable is always the = ops field of a io_pgtable. > + unsafe { kernel::container_of!(self.raw_ops(), = bindings::io_pgtable, ops) } > + } > + > + /// Obtain a raw pointer to the underlying `struct = io_pgtable_cfg`. > + #[inline] > + pub fn raw_cfg(&self) -> *mut bindings::io_pgtable_cfg { > + // SAFETY: The `raw_pgtable()` method returns a valid = pointer. > + unsafe { &raw mut (*self.raw_pgtable()).cfg } > + } > + I don=E2=80=99t think that drivers need these three accessors above to = be pub. > + /// Map a physically contiguous range of pages of the same size. > + /// > + /// # Safety > + /// > + /// * This page table must not contain any mapping that overlaps = with the mapping created by > + /// this call. I don't think there is a restriction that forbids you from mapping a = region that has already been mapped. If A->B->C are adjacent regions, and you try to map A -> C when B->C is = already mapped, I think this call will simply return length(A->B). > + /// * If this page table is live, then the caller must ensure = that it's okay to access the > + /// physical address being mapped for the duration in which it = is mapped. > + #[inline] > + pub unsafe fn map_pages( > + &self, > + iova: usize, > + paddr: PhysAddr, > + pgsize: usize, > + pgcount: usize, > + prot: u32, > + flags: alloc::Flags, > + ) -> Result { > + let mut mapped: usize =3D 0; > + > + // SAFETY: The `map_pages` function in `io_pgtable_ops` is = never null. > + let map_pages =3D unsafe { = (*self.raw_ops()).map_pages.unwrap_unchecked() }; > + > + // SAFETY: The safety requirements of this method are = sufficient to call `map_pages`. > + to_result(unsafe { > + (map_pages)( > + self.raw_ops(), > + iova, > + paddr, > + pgsize, > + pgcount, > + prot as i32, > + flags.as_raw(), > + &mut mapped, > + ) > + })?; > + > + Ok(mapped) > + } > + > + /// Unmap a range of virtually contiguous pages of the same size. > + /// > + /// # Safety > + /// > + /// This page table must contain a mapping at `iova` that = consists of exactly `pgcount` pages > + /// of size `pgsize`. Same here. I don=E2=80=99t think the above is necessarily a requirement. > + #[inline] > + pub unsafe fn unmap_pages(&self, iova: usize, pgsize: usize, = pgcount: usize) -> usize { > + // SAFETY: The `unmap_pages` function in `io_pgtable_ops` is = never null. > + let unmap_pages =3D unsafe { = (*self.raw_ops()).unmap_pages.unwrap_unchecked() }; > + > + // SAFETY: The safety requirements of this method are = sufficient to call `unmap_pages`. > + unsafe { (unmap_pages)(self.raw_ops(), iova, pgsize, pgcount, = core::ptr::null_mut()) } > + } > +} > + > +// These bindings are currently designed for use by GPU drivers, = which use this page table together > +// with GPUVM. When using GPUVM, a single mapping operation may be = translated into many operations > +// on the page table, and in that case you generally want to flush = the TLB only once per GPUVM > +// operation. Thus, do not use these callbacks as they would flush = more often than needed. > +static NOOP_FLUSH_OPS: bindings::iommu_flush_ops =3D = bindings::iommu_flush_ops { > + tlb_flush_all: Some(rust_tlb_flush_all_noop), > + tlb_flush_walk: Some(rust_tlb_flush_walk_noop), > + tlb_add_page: None, > +}; > + > +#[no_mangle] > +extern "C" fn rust_tlb_flush_all_noop(_cookie: *mut = core::ffi::c_void) {} > + > +#[no_mangle] > +extern "C" fn rust_tlb_flush_walk_noop( > + _iova: usize, > + _size: usize, > + _granule: usize, > + _cookie: *mut core::ffi::c_void, > +) { > +} > + > +impl Drop for IoPageTable { > + fn drop(&mut self) { > + // SAFETY: The caller of `ttbr` promised that the page table = is not live when this > + // destructor runs. > + unsafe { bindings::free_io_pgtable_ops(self.0.ops) }; > + } > +} > + > +/// The `ARM_64_LPAE_S1` page table format. > +pub enum ARM64LPAES1 {} > + > +impl IoPageTableFmt for ARM64LPAES1 { > + const FORMAT: io_pgtable_fmt =3D = bindings::io_pgtable_fmt_ARM_64_LPAE_S1 as io_pgtable_fmt; > +} > + > +impl IoPageTable { > + /// Access the `ttbr` field of the configuration. > + /// > + /// This is the physical address of the page table, which may be = passed to the device that > + /// needs to use it. > + /// > + /// # Safety > + /// > + /// The caller must ensure that the device stops using the page = table before dropping it. > + #[inline] > + pub unsafe fn ttbr(&self) -> u64 { > + // SAFETY: `arm_lpae_s1_cfg` is the right cfg type for = `ARM64LPAES1`. > + unsafe { = (*self.raw_cfg()).__bindgen_anon_1.arm_lpae_s1_cfg.ttbr } > + } > + > + /// Access the `mair` field of the configuration. > + #[inline] > + pub fn mair(&self) -> u64 { > + // SAFETY: `arm_lpae_s1_cfg` is the right cfg type for = `ARM64LPAES1`. > + unsafe { = (*self.raw_cfg()).__bindgen_anon_1.arm_lpae_s1_cfg.mair } > + } The two above will indeed be used by drivers, so it makes sense for them = to be pub. > +} >=20 > --- > base-commit: ffee675aceb9f44b0502a8bec912abb0c4f4af62 > change-id: 20251111-io-pgtable-fe0822b4ebdd > prerequisite-change-id: = 20251106-resource-phys-typedefs-6db37927d159:v2 > prerequisite-patch-id: 350421d8dbaf3db51b1243d82077c5eb88f54db5 > prerequisite-patch-id: ac0166fb3cd235de76841789173051191a4d2434 > prerequisite-patch-id: f4bca02c77c40093690b66cdf477f928784bdbf4 > prerequisite-patch-id: 083d1c22b1a7eb0dcae37052b926362543c68e8a >=20 > Best regards, > --=20 > Alice Ryhl >=20 >=20 This overall looks ok to me, and I quite like how much cleaner it is = now. However, I think a discussion will naturally emerge from making map/unmap_pages unsafe functions, and it seems like the safety = requirements do not apply. =E2=80=94 Daniel=