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bh=hNGWZZ5ZQKrAynm2JoLziPZQiNLOegDYK5Oz85U3bzA=; b=JoYvkrUK9bl9Xry93jw39ahjcIcjSiolR/z+Ozgo8290m1rW2k0RCFDbe96k8y2Zwq5bNR gCYXVNk5odCTEoj6xoo7u43vvrIm6UsPOOk0BKBO7owCgnCYowKVhiYIkwLR00RSOxQsy8 2OCy7IkrBKne7NDoFrGWE3jZCgzn7xc9AZQ85Sj4lDBsN/v8hcRgR4ogw/9XjYSq23sD3y KOwsJ9kjc9wDFKpW0PEPcB0QWP7/paC1wFUCC95sgriKRFh68IpQsUHKnHfOphyYboNNS6 RtrhDpJ7sp/K20t95xH6K0zrmxnpOCAkfJ5EfLWMLgbsz0HUzYEDUmHLh0vYJw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722417306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=hNGWZZ5ZQKrAynm2JoLziPZQiNLOegDYK5Oz85U3bzA=; b=ZubrFjMKtjGonD/DvEWn82TfhmSaYYOKHVTimUeiK5D34/6+X0iIX1mYj2P+hSTUHWi9fk uhRUIC+l5vrr5/BQ== To: 20240621164406.256314-1-kirill.shutemov@linux.intel.com, kirill.shutemov@linux.intel.com Cc: ardb@kernel.org, bp@alien8.de, brijesh.singh@amd.com, corbet@lwn.net, dave.hansen@linux.intel.com, hpa@zytor.com, jan.kiszka@siemens.com, jgross@suse.com, kbingham@kernel.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, luto@kernel.org, michael.roth@amd.com, mingo@redhat.com, peterz@infradead.org, rick.p.edgecombe@intel.com, sandipan.das@amd.com, thomas.lendacky@amd.com, x86@kernel.org Subject: Re: [PATCH 0/3] x86: Make 5-level paging support unconditional for x86-64 In-Reply-To: <80734605-1926-4ac7-9c63-006fe3ea6b6a@amd.com> References: <80734605-1926-4ac7-9c63-006fe3ea6b6a@amd.com> Date: Wed, 31 Jul 2024 11:15:05 +0200 Message-ID: <87wml16hye.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-Rspam-User: X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: B3D5440016 X-Stat-Signature: x4ra8bbstdnjzpzw1snxwusffzwhqdp5 X-HE-Tag: 1722417308-754602 X-HE-Meta: U2FsdGVkX1+o/uo3U4BrMWdmSwHCWLGXDy9C3pf5mIGT2DM4XcwR2nSa7HTrjSVTvb6nu43fJ8PAQxZtYPBP6MIRajYP67p8a7dodfpoA8vt1SVfBitBBNKk3k8lzr0/b+2Y9QJknwNQNHNW3b2t3H3hsv4N6mcmkEnXIbCWOAdxgj84qLAItX+Ixe2W/LbqFPpq+/LEjhV5mD5OLAV/MD8u9iDEZfYKLcnC9B6MlMrlDkzFfGwchjHx9wI5dUs+5SgppxWYCpODaRgRoDvevxNtFklBEKRsLUlN2WJV/He54NSp7xg/8nTRiQe9D5unMm/ioIR0mvrR3QHO2opLzTzTY4nk93HNlOc3FlWq/iyXXEaoOBceiNLifwPrZgwlFm/asfjUEGFpwUXLa4AOwfU/2T+bdxXs1P5WyWtfgJNHyFPzelKqjcuhv7s6ywUMXja/NbqA8iFAmincqtcV/mw55JJcZI1GJwbnm0kRbSpG7YNg8AjPSCIPB+io5v81icB+RYBAFo2goffx7/H87ao1+vgVyCfdfSIECVXlsw6knyhb5JmL0AwDSI6aoMLtWLPKFMHL6gUKfWXoQZEAFgG3+iVXO22jGBMLiexpAUg/qDv0YYgUKIzItZqp82hdQr4fxVek8KU/Fgtf+IkOvIEog9fwKSHNRskv7gR4LXmIhssJBben2C/eqKXsJYeJsm2DH7BFon26Zlclr44Cf9tLxibhyFgaeCGnIr0kHMECZ3pMA2K2zUHXwWC724D5KTO1GdfEUdDC96rKHdtaf1Q+lXkUP+JZgYhyiOK6m88mAgnHoQ+UX7xcWgUaULdleUggtNEV163cCBLZhnlNov1meVYCNfEP1fWwWTNBBhLy3eK2g6pMRE7pX6V14GKlrn8TBafm7vBxgYtDtgoX1pEFyvkxXrd72YZjoPGifGqK7nXokY88G7IGvGK3cjhzMn+7fDVtUOcoo+exlKp xk5PwD54 FI57aSnyI8KkWuSELQpe5H2qTj1ZkywE/Z/+YCnkWFSZfrDXSDKAJMqfVDsZzQtTr9vrYk9LhcI6S5rATLIUwjTa2KP8bbUZki61bhDcghFDUvQcucH7gSP/qen9no+S0DEHk X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Wed, Jul 31 2024 at 14:27, Shivank Garg wrote: > lmbench:lat_pagefault: Metric- page-fault time (us) - Lower is better > 4-Level PT 5-Level PT % Change > THP-never Mean:0.4068 Mean:0.4294 5.56 > 95% CI:0.4057-0.4078 95% CI:0.4287-0.4302 > > THP-Always Mean: 0.4061 Mean: 0.4288 % Change > 95% CI: 0.4051-0.4071 95% CI: 0.4281-0.4295 5.59 > > Inference: > 5-level page table shows increase in page-fault latency but it does > not significantly impact other benchmarks. 5% regression on lmbench is a NONO. 5-level page tables add a cost in every hardware page table walk. That's a matter of fact and there is absolutely no reason to inflict this cost on everyone. The solution to this to make the 5-level mechanics smarter by evaluating whether the machine has enough memory to require 5-level tables and select the depth at boot time. Thanks, tglx