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McKenney" , ryan.roberts@arm.com, chrisl@kernel.org Subject: Re: Can you help us on memory barrier usage? (was Re: [PATCH v4 4/6] mm: swap: Allow storage of all mTHP orders) In-Reply-To: (Akira Yokosawa's message of "Sat, 23 Mar 2024 11:11:09 +0900") References: <87r0g3q9cz.fsf_-_@yhuang6-desk2.ccr.corp.intel.com> Date: Mon, 25 Mar 2024 11:00:28 +0800 Message-ID: <87v85bow1f.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) MIME-Version: 1.0 Content-Type: text/plain; charset=ascii X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 7820D1C0009 X-Stat-Signature: sj39pbchoauhxbrtaznt5d4cbg8ayzmn X-HE-Tag: 1711335744-560922 X-HE-Meta: U2FsdGVkX1/iox4EJzrymwB52K3QN5Zl2YQGQbblHd5mykGPTYI/6WHi54nbcDsMTFwBkzZiwW9b9O1Myn9DdWxikD/0KTM38UIJBFjR9TIanvlYbhJTuHpzo9OqehKDqKE+6ZEKHcNLCHBaYAICdL3bYN+u46twSgBXYlMGl5jnVtHf8TAg6fZMGSSBS9xj5ClM9WWM/Gb2iWK2pPiGmSBxPP0y1JgmFHzqrDaoQBRUCPg2P3xT/ov/F9o8xUKacWb65/44XGS7EpPJbQUCXcuEnl1Ff2T3d+SQ16dg74nmEbnp2HxnIOdQW/aRXpCGZw/YIK5eaVfekAKzZSU8gJ+UXb1q+aodV52cFsCbMKEiP0tILInVfQ3pTx8f2FXv8vP/kR83PBKcaKMl9dMcOdir6i73ATeBaY50YJHuEbB/ogwtkGUrhYGGjf4F23kGC/puwxlnVslT4aZ8yczHmMW5nV3aTjzsB0mhAhQwaC79/hCzip0gko5gv3Zqvm4AMRQEcQErp2JkIAN4MYB7VoRf+96a6OufM9ffRiaufwbwgkV29fu7u8aixqrqSfhwkJXmK1OJnuiJituWfTqpOZiGIv1z9yEYfdjxkTVAJRXeNfKe1ysmgOW+aMYFMdD2ie3PlxX0P3OaJnzKvNzDfz26SXOiDU3tCLl/OVY4cmxIP5BbeY40Sbjd6tWxpKmBfBetf9EfcWRYNh7GaaVmlREnqppk4tyZme5JNt+P3GqHB8SvHkmAu/Qubto+JEXGyW2eQSnCAE2Us2FwlTP79F0ZHk9dMAteYkBQKvLhLszKGExf5qQsslVVEaPv9z45+T0HrGnImYeQjlNmvL8zahy0Bq753rc4CQ202IUmPz8OXM0Br1ruu8wBdnc6MUrZgvsQwSMo5vJSVybE+IVwNykdUgWkoWlXKnIf+MlBaNNwrW5RykanCBqf8U8AKWvXBQS5QbBbJR7rM37SuIK YubJpRaW Z8Yhuau/t1Jc9cJ5MmnCCWTLkbHnRrUH1lO/UwRNjFhkhjnRlDAT9TsRVa1M+/yGGIQn4AWugPsCsD7Yhz7Zpo4v+OHYKO62XzTNy8gesHwxtAVbO0g2uWHEAiEQ1taXXg+1qhnpBRVm+of3qi6V+3Ys3bB8jFGYUw5RrSlzOJPIWYmHJ9WnzYI1UJWJokcN9DFYVNUK/qQKaCBuxCkdI+vvhX9OmHPtesuRjbuSv4Pr+qH7OxoeX2lI6bQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Akira Yokosawa writes: > [Use Paul's reachable address in CC; > trimmed CC list, keeping only those who have responded so far.] Thanks a lot! > Hello Huang, > Let me chime in. > > On Fri, 22 Mar 2024 06:19:52 -0700, Huang, Ying wrote: >> Hi, Paul, >> >> Can you help us on WRITE_ONCE()/READ_ONCE()/barrier() usage as follows? >> For some example kernel code as follows, >> >> " >> unsigned char x[16]; >> >> void writer(void) >> { >> memset(x, 1, sizeof(x)); >> /* To make memset() take effect ASAP */ >> barrier(); >> } >> >> unsigned char reader(int n) >> { >> return READ_ONCE(x[n]); >> } >> " >> >> where, writer() and reader() may be called on 2 CPUs without any lock. >> It's acceptable for reader() to read the written value a little later. >> Our questions are, >> >> 1. because it's impossible for accessing "unsigned char" to cause >> tearing. So, WRITE_ONCE()/READ_ONCE()/barrier() isn't necessary for >> correctness, right? >> >> 2. we use barrier() and READ_ONCE() in writer() and reader(), because we >> want to make writing take effect ASAP. Is it a good practice? Or it's >> a micro-optimization that should be avoided? > > Why don't you consult Documentation/memory-barriers.txt, especially > the section titled "COMPILER BARRIER"? > > TL;DR: > > barrier(), WRITE_ONCE(), and READ_ONCE() are compiler barriers, not > memory barriers. They just restrict compiler optimizations and don't > have any effect with regard to "make writing take effect ASAP". Yes. In theory, this is absolutely correct. My question is, in practice, will compiler barriers make CPU runs (or sees) memory read/write instructions a little earlier via avoiding to reorder the operations after read/write (e.g., becomes before read/write)? > If you have further questions, please don't hesitate to ask. -- Best Regards, Huang, Ying