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X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="332471102" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="332471102" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2023 18:51:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="812802717" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="812802717" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2023 18:51:50 -0700 From: "Huang, Ying" To: Nadav Amit Cc: Andrew Morton , "linux-mm@kvack.org" , "linux-kernel@vger.kernel.org" , kernel test robot , "Mel Gorman" , Hugh Dickins , Matthew Wilcox , David Hildenbrand Subject: Re: [PATCH] mm,unmap: avoid flushing TLB in batch if PTE is inaccessible References: <20230410075224.827740-1-ying.huang@intel.com> <402A3E9D-5136-4747-91FF-C3AA2D557784@vmware.com> <87zg7f19xu.fsf@yhuang6-desk2.ccr.corp.intel.com> Date: Wed, 12 Apr 2023 09:50:40 +0800 In-Reply-To: (Nadav Amit's message of "Tue, 11 Apr 2023 17:52:02 +0000") Message-ID: <87sfd5zx5b.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Rspam-User: X-Rspamd-Queue-Id: 5A86BA0006 X-Rspamd-Server: rspam01 X-Stat-Signature: 8c3oq738nx7ujyf94okbzdxrkdks87dz X-HE-Tag: 1681264315-81261 X-HE-Meta: U2FsdGVkX1/8oodit1Sx3JntiP39aKp8CsvAdfiMQK4opuSetlo8K4V9PTcEFcjRLfqWjFYrFUoFlzktLrq8kPpCnwMkBbkvwFugX8oCBj9svGEpFBXqFkVSkRhW6/rKdtkWA/npcdTbE1IEKuDAJVVJuNiJcXl/p+NEt2+9qfnOVPTUpooPIwbOgxXVqeYPCbK073cg7TYEbm+85zPWJEiDRic/h16wTZ8IO4npXFaj5kh2h0dSV7az412AH4/zhNqmJGEfdN2LaEGQatkcYhFi/MrIqj34qg8ko0FUi/yOcRPKU3HN/+0l7fI5cgik33Zftz0ru7wW1Muugm+uqDj4cVzAo5ytmq66mqog6L4H4cFbE4ZmTnOjGHUR9JCiNAW2EgZQx3wePmlku1fiOHdw2URtf2a4L7N+MA2dYUwYje+x+WdSYfLnyiY4t9nR3T8igZi5kGMm9hfCtrfwzzKwjqtQFwHa3X+pPmpnXbQmWuvRbG/HhWsB0pRNe5zuPJL/JzoKUVyz6oqbCTmzdQtdD4fDg/6tGl238tnHGx8SwYwM+/n/vC4LhCazJVoKZFM4xyKtFACqZohbRGTgHe4Z7Eb/x0iXtSECC/jia/nUjWLzof6XRTL1eRCKdhHdAX4MPzYvMeHS5cjNMpzXmCAmmO93wygiQiD5y2HR6CMGA9UCbpJRuffrGk8GsR4NtibE/dnpNlXWYrHzYGgkU5rtx6Q8jHpt0J2G9mFDc9y0jWS7YMT9X3bVWs/EzYGSm4ajltHC0Bb2fu+iK+T8X2MOV2W+Eh0eoF28KQJQRKmF31zduwETCiTeBRLyyYIVeHXJhnwE6iFuap+tPL8/2yY+c3LHlUZ/KEC/SEKVEiMDZ+3mCmJvII0pZiWjDfinoV13CiW3qXOxaIgIX340JjUwRPWBI6RHLpzvL3asEflcSLhDdkkGA5VQDZh19ZFklMRmjTMnj7kAcLJvoMq SGSZW4fM jC/zIpm/NaaAjRaTvs/3CKmoYDZ8sqLOisHJ0U49aVPeFKgDvhV5zoOi0/M1WeIdKOcR43VDhrJw52xJOny85yRkuDhYUgWqxOcobYkpgSbhn0I87c6996kQ+VQFOLlpYK3+sY2TiAEZFXiZ9QMbEf2I9B3Yksd1iIy+eVk2loUmK7CSvLSgRENZc04CN1QApMK4Fby6WadPFp1m5IA+Xn/MFkQifwkLxG0s8Yh6Xs2r7bJxoEo71xJOPLFM0gKRdjjgyiOR5IhVVx+qTHJx5qa3cEQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Nadav Amit writes: >> On Apr 10, 2023, at 6:31 PM, Huang, Ying wrote: >>=20 >> !! External Email >>=20 >> Hi, Amit, >>=20 >> Thank you very much for review! >>=20 >> Nadav Amit writes: >>=20 >>>> On Apr 10, 2023, at 12:52 AM, Huang Ying wrote: >>>>=20 >>>> 0Day/LKP reported a performance regression for commit >>>> 7e12beb8ca2a ("migrate_pages: batch flushing TLB"). In the commit, the >>>> TLB flushing during page migration is batched. So, in >>>> try_to_migrate_one(), ptep_clear_flush() is replaced with >>>> set_tlb_ubc_flush_pending(). In further investigation, it is found >>>> that the TLB flushing can be avoided in ptep_clear_flush() if the PTE >>>> is inaccessible. In fact, we can optimize in similar way for the >>>> batched TLB flushing too to improve the performance. >>>>=20 >>>> So in this patch, we check pte_accessible() before >>>> set_tlb_ubc_flush_pending() in try_to_unmap/migrate_one(). Tests show >>>> that the benchmark score of the anon-cow-rand-mt test case of >>>> vm-scalability test suite can improve up to 2.1% with the patch on a >>>> Intel server machine. The TLB flushing IPI can reduce up to 44.3%. >>>=20 >>> LGTM. >>=20 >> Thanks! >>=20 >>> I know it=E2=80=99s meaningless for x86 (but perhaps ARM would use this= infra >>> too): do we need smp_mb__after_atomic() after ptep_get_and_clear() and >>> before pte_accessible()? >>=20 >> Why do we need the memory barrier? IIUC, the PTL is locked, so PTE >> value will not be changed under us. Anything else? > > I was thinking about the ordering with respect to > atomic_read(&mm->tlb_flush_pending), which is not protected by the PTL. > I guess you can correctly argue that because of other control-flow > dependencies, the barrier is not necessary. For ordering between ptep_get_and_clear() and atomic_read(&mm->tlb_flush_pending), I think PTL has provided the necessary protection already. The code path to write mm->tlb_flush_pending is, tlb_gather_mmu inc_tlb_flush_pending a) lock PTL change PTE b) unlock PTL tlb_finish_mmu dec_tlb_flush_pending c) While code path of try_to_unmap/migrate_one is, lock PTL read and change PTE d) read mm->tlb_flush_pending e) unlock PTL Even if e) occurs before d), they cannot occur at the same time of b). Do I miss anything? Best Regards, Huang, Ying [snip]