From: "Huang, Ying" <ying.huang@intel.com>
To: Peter Xu <peterx@redhat.com>
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org,
Minchan Kim <minchan@kernel.org>,
David Hildenbrand <david@redhat.com>,
Nadav Amit <nadav.amit@gmail.com>,
Andrew Morton <akpm@linux-foundation.org>,
Hugh Dickins <hughd@google.com>,
Vlastimil Babka <vbabka@suse.cz>,
Andrea Arcangeli <aarcange@redhat.com>,
Andi Kleen <andi.kleen@intel.com>,
"Kirill A . Shutemov" <kirill@shutemov.name>
Subject: Re: [PATCH v3 5/7] mm: Remember young/dirty bit for page migrations
Date: Fri, 12 Aug 2022 10:32:48 +0800 [thread overview]
Message-ID: <87pmh6dwdr.fsf@yhuang6-desk2.ccr.corp.intel.com> (raw)
In-Reply-To: <YvUeB0jc6clz59z5@xz-m1.local> (Peter Xu's message of "Thu, 11 Aug 2022 11:19:35 -0400")
Peter Xu <peterx@redhat.com> writes:
> On Tue, Aug 09, 2022 at 06:00:58PM -0400, Peter Xu wrote:
>> diff --git a/mm/migrate_device.c b/mm/migrate_device.c
>> index 27fb37d65476..699f821b8443 100644
>> --- a/mm/migrate_device.c
>> +++ b/mm/migrate_device.c
>> @@ -221,6 +221,10 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
>> else
>> entry = make_readable_migration_entry(
>> page_to_pfn(page));
>> + if (pte_young(pte))
>> + entry = make_migration_entry_young(entry);
>> + if (pte_dirty(pte))
>> + entry = make_migration_entry_dirty(entry);
>> swp_pte = swp_entry_to_pte(entry);
>> if (pte_present(pte)) {
>> if (pte_soft_dirty(pte))
>
> This change needs to be wrapped with pte_present() at least..
>
> I also just noticed that this change probably won't help anyway because:
>
> (1) When ram->device, the pte will finally be replaced with a device
> private entry, and device private entry does not yet support A/D, it
> means A/D will be dropped again,
>
> (2) When device->ram, we are missing information on either A/D bits, or
> even if device private entries start to suport A/D, it's still not
> clear whether we should take device read/write into considerations
> too on the page A/D bits to be accurate.
>
> I think I'll probably keep the code there for completeness, but I think it
> won't really help much until more things are done.
It appears that there are more issues. Between "pte = *ptep" and pte
clear, CPU may set A/D bit in PTE, so we may need to update pte when
clearing PTE. And I don't find the TLB is flushed in some cases after
PTE is cleared.
Best Regards,
Huang, Ying
next prev parent reply other threads:[~2022-08-12 2:33 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-09 22:00 [PATCH v3 0/7] mm: Remember a/d bits for migration entries Peter Xu
2022-08-09 22:00 ` [PATCH v3 1/7] mm/x86: Use SWP_TYPE_BITS in 3-level swap macros Peter Xu
2022-08-10 1:13 ` Huang, Ying
2022-08-09 22:00 ` [PATCH v3 2/7] mm/swap: Comment all the ifdef in swapops.h Peter Xu
2022-08-10 1:19 ` Huang, Ying
2022-08-09 22:00 ` [PATCH v3 3/7] mm/swap: Add swp_offset_pfn() to fetch PFN from swap entry Peter Xu
2022-08-10 6:04 ` Huang, Ying
2022-08-10 13:17 ` Peter Xu
2022-08-09 22:00 ` [PATCH v3 4/7] mm/thp: Carry over dirty bit when thp splits on pmd Peter Xu
2022-08-10 6:24 ` Huang, Ying
2022-08-10 15:13 ` Peter Xu
2022-08-09 22:00 ` [PATCH v3 5/7] mm: Remember young/dirty bit for page migrations Peter Xu
2022-08-10 6:30 ` Huang, Ying
2022-08-10 15:19 ` Peter Xu
2022-08-11 15:19 ` Peter Xu
2022-08-12 2:32 ` Huang, Ying [this message]
2022-08-15 19:18 ` Peter Xu
2022-08-15 20:52 ` Nadav Amit
2022-08-15 21:03 ` Nadav Amit
2022-08-18 16:39 ` Dave Hansen
2022-08-17 1:49 ` Huang, Ying
2022-08-09 22:00 ` [PATCH v3 6/7] mm/swap: Cache maximum swapfile size when init swap Peter Xu
2022-08-10 6:33 ` Huang, Ying
2022-08-10 13:23 ` Peter Xu
2022-08-09 22:01 ` [PATCH v3 7/7] mm/swap: Cache swap migration A/D bits support Peter Xu
2022-08-10 6:37 ` Huang, Ying
2022-08-10 17:09 ` Peter Xu
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