From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9085CC19F2D for ; Wed, 10 Aug 2022 01:13:53 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 151858E0002; Tue, 9 Aug 2022 21:13:53 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 1015B8E0001; Tue, 9 Aug 2022 21:13:53 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id F0A4A8E0002; Tue, 9 Aug 2022 21:13:52 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id E05AA8E0001 for ; Tue, 9 Aug 2022 21:13:52 -0400 (EDT) Received: from smtpin26.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay05.hostedemail.com (Postfix) with ESMTP id B77EA40477 for ; Wed, 10 Aug 2022 01:13:52 +0000 (UTC) X-FDA: 79781911104.26.CC0549B Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by imf25.hostedemail.com (Postfix) with ESMTP id 0DD3EA0058 for ; Wed, 10 Aug 2022 01:13:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660094032; x=1691630032; h=from:to:cc:subject:references:date:in-reply-to: message-id:mime-version; bh=8Xge/9Yr6O6A+kIvlPS10YwFvkruFukln1LqLT800M8=; b=ZjSEYZb/YwXTuHptGFS/LZ9b/W0CxVEJ6+sS+kQqGauA8/K7wbx3bYU+ FyH48zmxOftp97KHHORSJw+yjOuSwibuaty+4ioPrzYYtN27faZTrDFGO gkdCF7vw+9UynyGuSHHAT6MJheNiljRN0DI6OP45biQLI17b5UZkWgv7i JS/DM7zYOc8Ulw2hc0pvDfxLV7TR1twrxl+pAv88JDq/aSS+vgDLlc0TK FA7u0WAl+N/OqWnxIrS+1oXV62BoQuZWVMlso73rCXm7jWJj9gLl2B7iq 4mTG6x5JJcvXWJ01Ev69KlKOl00KpEXhs4ipCDva3lexevZCcPsUAeuDS g==; X-IronPort-AV: E=McAfee;i="6400,9594,10434"; a="292217264" X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="292217264" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 18:13:50 -0700 X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="673104676" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 18:13:47 -0700 From: "Huang, Ying" To: Peter Xu Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Minchan Kim , David Hildenbrand , Nadav Amit , Andrew Morton , Hugh Dickins , Vlastimil Babka , Andrea Arcangeli , Andi Kleen , "Kirill A . Shutemov" Subject: Re: [PATCH v3 1/7] mm/x86: Use SWP_TYPE_BITS in 3-level swap macros References: <20220809220100.20033-1-peterx@redhat.com> <20220809220100.20033-2-peterx@redhat.com> Date: Wed, 10 Aug 2022 09:13:44 +0800 In-Reply-To: <20220809220100.20033-2-peterx@redhat.com> (Peter Xu's message of "Tue, 9 Aug 2022 18:00:54 -0400") Message-ID: <87k07ggat3.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=ascii ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1660094032; a=rsa-sha256; cv=none; b=hjNPI77+S9FhUpa6vqIlzIFIuprrXpjj81HShTI0SifIs8myuCW5qrbszYVVnMtez5jQ/T I1GbAzlwgFHQr6H6Q3M0JwkVnpCN9D+UEcP4UpvYiSdncPF151xKe+/WJ0H2EiI8UAwjxZ hqaVe8pHdV+E4/rcpHfsw52BVWbpCNA= ARC-Authentication-Results: i=1; imf25.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b="ZjSEYZb/"; spf=pass (imf25.hostedemail.com: domain of ying.huang@intel.com designates 134.134.136.65 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1660094032; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=rAdkm0s0aXXQgOeOjGsWLq/vMKAhpp3hKarOwCwXh0g=; b=OsOMQOpZEKGv9UrBdisQs95uEl4BO3FbOPwXTdFtczqbAXcpxulHxS1d9msJ0gDGyPDS0K LxWsDuCgvSiMC2oNKwymRm0sbqTfcmdWvEqDRyKUo6El7VIsA3krkkP1hIVmljf6yMpWzB hYlkt90NAsn4tSLMfAe/d/xWVHINXXs= X-Rspamd-Queue-Id: 0DD3EA0058 Authentication-Results: imf25.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b="ZjSEYZb/"; spf=pass (imf25.hostedemail.com: domain of ying.huang@intel.com designates 134.134.136.65 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com X-Rspamd-Server: rspam09 X-Rspam-User: X-Stat-Signature: ypsgyo8wejqzm9dinzt1yroo9h53mqw4 X-HE-Tag: 1660094031-80582 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Peter Xu writes: > Replace all the magic "5" with the macro. > > Reviewed-by: David Hildenbrand > Signed-off-by: Peter Xu Reviewed-by: "Huang, Ying" Best Regards, Huang, Ying > --- > arch/x86/include/asm/pgtable-3level.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h > index e896ebef8c24..28421a887209 100644 > --- a/arch/x86/include/asm/pgtable-3level.h > +++ b/arch/x86/include/asm/pgtable-3level.h > @@ -256,10 +256,10 @@ static inline pud_t native_pudp_get_and_clear(pud_t *pudp) > /* We always extract/encode the offset by shifting it all the way up, and then down again */ > #define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS) > > -#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5) > -#define __swp_type(x) (((x).val) & 0x1f) > -#define __swp_offset(x) ((x).val >> 5) > -#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5}) > +#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) > +#define __swp_type(x) (((x).val) & ((1UL << SWP_TYPE_BITS) - 1)) > +#define __swp_offset(x) ((x).val >> SWP_TYPE_BITS) > +#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << SWP_TYPE_BITS}) > > /* > * Normally, __swp_entry() converts from arch-independent swp_entry_t to