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[203.11.71.1]) by mx.google.com with ESMTPS id u11si1183467plq.287.2019.01.30.02.52.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 30 Jan 2019 02:52:43 -0800 (PST) Received-SPF: neutral (google.com: 203.11.71.1 is neither permitted nor denied by best guess record for domain of mpe@ellerman.id.au) client-ip=203.11.71.1; Authentication-Results: mx.google.com; spf=neutral (google.com: 203.11.71.1 is neither permitted nor denied by best guess record for domain of mpe@ellerman.id.au) smtp.mailfrom=mpe@ellerman.id.au Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPSA id 43qKvW28qXz9s3q; Wed, 30 Jan 2019 21:52:39 +1100 (AEDT) From: Michael Ellerman To: "Aneesh Kumar K.V" , npiggin@gmail.com, benh@kernel.crashing.org, paulus@samba.org, akpm@linux-foundation.org, x86@kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-mm@kvack.org, "Aneesh Kumar K.V" Subject: Re: [PATCH V5 3/5] arch/powerpc/mm: Nest MMU workaround for mprotect RW upgrade. In-Reply-To: <20190116085035.29729-4-aneesh.kumar@linux.ibm.com> References: <20190116085035.29729-1-aneesh.kumar@linux.ibm.com> <20190116085035.29729-4-aneesh.kumar@linux.ibm.com> Date: Wed, 30 Jan 2019 21:52:38 +1100 Message-ID: <87fttaqux5.fsf@concordia.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: "Aneesh Kumar K.V" writes: > NestMMU requires us to mark the pte invalid and flush the tlb when we do a > RW upgrade of pte. We fixed a variant of this in the fault path in commit > Fixes: bd5050e38aec ("powerpc/mm/radix: Change pte relax sequence to handle nest MMU hang") You don't want the "Fixes:" there. > > Do the same for mprotect upgrades. > > Hugetlb is handled in the next patch. > > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/book3s/64/pgtable.h | 18 ++++++++++++++ > arch/powerpc/include/asm/book3s/64/radix.h | 4 ++++ > arch/powerpc/mm/pgtable-book3s64.c | 25 ++++++++++++++++++++ > arch/powerpc/mm/pgtable-radix.c | 18 ++++++++++++++ > 4 files changed, 65 insertions(+) > > diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h > index 2e6ada28da64..92eaea164700 100644 > --- a/arch/powerpc/include/asm/book3s/64/pgtable.h > +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h > @@ -1314,6 +1314,24 @@ static inline int pud_pfn(pud_t pud) > BUILD_BUG(); > return 0; > } Can we get a blank line here? > +#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION > +pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); > +void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, > + pte_t *, pte_t, pte_t); So these are not inline ... > +/* > + * Returns true for a R -> RW upgrade of pte > + */ > +static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) > +{ > + if (!(old_val & _PAGE_READ)) > + return false; > + > + if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) > + return true; > + > + return false; > +} > > #endif /* __ASSEMBLY__ */ > #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ > diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c > index f3c31f5e1026..47c742f002ea 100644 > --- a/arch/powerpc/mm/pgtable-book3s64.c > +++ b/arch/powerpc/mm/pgtable-book3s64.c > @@ -400,3 +400,28 @@ void arch_report_meminfo(struct seq_file *m) > atomic_long_read(&direct_pages_count[MMU_PAGE_1G]) << 20); > } > #endif /* CONFIG_PROC_FS */ > + > +pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, > + pte_t *ptep) > +{ > + unsigned long pte_val; > + > + /* > + * Clear the _PAGE_PRESENT so that no hardware parallel update is > + * possible. Also keep the pte_present true so that we don't take > + * wrong fault. > + */ > + pte_val = pte_update(vma->vm_mm, addr, ptep, _PAGE_PRESENT, _PAGE_INVALID, 0); > + > + return __pte(pte_val); > + > +} > + > +void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, > + pte_t *ptep, pte_t old_pte, pte_t pte) > +{ Which means we're going to be doing a function call to get to here ... > + if (radix_enabled()) > + return radix__ptep_modify_prot_commit(vma, addr, > + ptep, old_pte, pte); And then another function call to get to the radix version ... > + set_pte_at(vma->vm_mm, addr, ptep, pte); > +} > diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c > index 931156069a81..dced3cd241c2 100644 > --- a/arch/powerpc/mm/pgtable-radix.c > +++ b/arch/powerpc/mm/pgtable-radix.c > @@ -1063,3 +1063,21 @@ void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, > } > /* See ptesync comment in radix__set_pte_at */ > } > + > +void radix__ptep_modify_prot_commit(struct vm_area_struct *vma, > + unsigned long addr, pte_t *ptep, > + pte_t old_pte, pte_t pte) > +{ > + struct mm_struct *mm = vma->vm_mm; > + > + /* > + * To avoid NMMU hang while relaxing access we need to flush the tlb before > + * we set the new value. We need to do this only for radix, because hash > + * translation does flush when updating the linux pte. > + */ > + if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) && > + (atomic_read(&mm->context.copros) > 0)) > + radix__flush_tlb_page(vma, addr); To finally get here, where we'll realise that 99.99% of processes don't use copros and so we have nothing to do except set the PTE. > + > + set_pte_at(mm, addr, ptep, pte); > +} So can we just make it all inline in the header? Or do we think it's not a hot enough path to worry about it? cheers