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17 Aug 2022 23:34:52 -0700 X-IronPort-AV: E=Sophos;i="5.93,245,1654585200"; d="scan'208";a="935680965" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 23:34:48 -0700 From: "Huang, Ying" To: Peter Xu Cc: Nadav Amit , Alistair Popple , huang ying , Linux MM , Andrew Morton , LKML , "Sierra Guiza, Alejandro (Alex)" , Felix Kuehling , Jason Gunthorpe , John Hubbard , David Hildenbrand , Ralph Campbell , Matthew Wilcox , Karol Herbst , Lyude Paul , Ben Skeggs , Logan Gunthorpe , paulus@ozlabs.org, linuxppc-dev@lists.ozlabs.org, stable@vger.kernel.org Subject: Re: [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page References: <6e77914685ede036c419fa65b6adc27f25a6c3e9.1660635033.git-series.apopple@nvidia.com> <871qtfvdlw.fsf@nvdebian.thelocal> <87o7wjtn2g.fsf@nvdebian.thelocal> <87tu6bbaq7.fsf@yhuang6-desk2.ccr.corp.intel.com> <1D2FB37E-831B-445E-ADDC-C1D3FF0425C1@gmail.com> Date: Thu, 18 Aug 2022 14:34:45 +0800 In-Reply-To: (Peter Xu's message of "Wed, 17 Aug 2022 15:27:32 -0400") Message-ID: <87czcyawl6.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; 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bh=g8FhtQu1Gf0lwdMlNQfHvyMKNYshi+G19JSSnM8kK8g=; b=e1ZYlAj8viQfcqg1L5xoaTm/EXBbGovH1Eb9Wcx9ULXWLFA4oQyHg9xFIlVAYlZM0c5V7Z XOpgD18HIgE+rbBjz0HSTTmP3fUalERhE9KypZYx7KFVdNKOEKUCzC+nSgF8rif/a2vYeI M+tfTo/U9v3mVqCn0QVwd00EJ0QJ1kk= Authentication-Results: imf07.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=dAXsHA5p; spf=pass (imf07.hostedemail.com: domain of ying.huang@intel.com designates 134.134.136.20 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com X-Rspam-User: X-Rspamd-Server: rspam12 X-Stat-Signature: j3qro9p7bfrwzksq4gjqaxtyy6z53y5z X-Rspamd-Queue-Id: 848424005C X-HE-Tag: 1660804494-26814 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Peter Xu writes: > On Wed, Aug 17, 2022 at 02:41:19AM -0700, Nadav Amit wrote: >> 4. Having multiple TLB flushing infrastructures makes all of these >> discussions very complicated and unmaintainable. I need to convince myse= lf >> in every occasion (including this one) whether calls to >> flush_tlb_batched_pending() and tlb_flush_pending() are needed or not. >>=20 >> What I would like to have [3] is a single infrastructure that gets a >> =E2=80=9Cticket=E2=80=9D (generation when the batching started), the old= PTE and the new PTE >> and checks whether a TLB flush is needed based on the arch behavior and = the >> current TLB generation. If needed, it would update the =E2=80=9Cticket= =E2=80=9D to the new >> generation. Andy wanted a ring for pending TLB flushes, but I think it i= s an >> overkill with more overhead and complexity than needed. >>=20 >> But the current situation in which every TLB flush is a basis for long >> discussions and prone to bugs is impossible. >>=20 >> I hope it helps. Let me know if you want me to revive the patch-set or o= ther >> feedback. >>=20 >> [1] https://lore.kernel.org/all/20220711034615.482895-5-21cnbao@gmail.co= m/ >> [2] https://lore.kernel.org/all/20220718120212.3180-13-namit@vmware.com/ >> [3] https://lore.kernel.org/all/20210131001132.3368247-16-namit@vmware.c= om/ > > I need more reading on tlb code and also [3] which looks useful to me. > It's definitely sad to make tlb flushing so complicated. It'll be great = if > things can be sorted out someday. > > In this specific case, the only way to do safe tlb batching in my mind is: > > pte_offset_map_lock(); > arch_enter_lazy_mmu_mode(); > // If any pending tlb, do it now > if (mm_tlb_flush_pending()) > flush_tlb_range(vma, start, end); > else > flush_tlb_batched_pending(); I don't think we need the above 4 lines. Because we will flush TLB before we access the pages. Can you find any issue if we don't use the above 4 lines? Best Regards, Huang, Ying > loop { > ... > pte =3D ptep_get_and_clear(); > ... > if (pte_present()) > unmapped++; > ... > } > if (unmapped) > flush_tlb_range(walk->vma, start, end); > arch_leave_lazy_mmu_mode(); > pte_unmap_unlock(); > > I may miss something, but even if not it already doesn't look pretty. > > Thanks,