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From: "Huang, Ying" <ying.huang@intel.com>
To: Peter Xu <peterx@redhat.com>
Cc: Nadav Amit <nadav.amit@gmail.com>,
	 Alistair Popple <apopple@nvidia.com>,
	 huang ying <huang.ying.caritas@gmail.com>,
	 Linux MM <linux-mm@kvack.org>,
	 Andrew Morton <akpm@linux-foundation.org>,
	 LKML <linux-kernel@vger.kernel.org>,
	 "Sierra Guiza, Alejandro (Alex)" <alex.sierra@amd.com>,
	 Felix Kuehling <Felix.Kuehling@amd.com>,
	 Jason Gunthorpe <jgg@nvidia.com>,
	 John Hubbard <jhubbard@nvidia.com>,
	 David Hildenbrand <david@redhat.com>,
	 Ralph Campbell <rcampbell@nvidia.com>,
	Matthew Wilcox <willy@infradead.org>,
	 Karol Herbst <kherbst@redhat.com>, Lyude Paul <lyude@redhat.com>,
	 Ben Skeggs <bskeggs@redhat.com>,
	 Logan Gunthorpe <logang@deltatee.com>,
	 paulus@ozlabs.org, linuxppc-dev@lists.ozlabs.org,
	 stable@vger.kernel.org
Subject: Re: [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page
Date: Thu, 18 Aug 2022 14:34:45 +0800	[thread overview]
Message-ID: <87czcyawl6.fsf@yhuang6-desk2.ccr.corp.intel.com> (raw)
In-Reply-To: <Yv1BJKb5he3dOHdC@xz-m1.local> (Peter Xu's message of "Wed, 17 Aug 2022 15:27:32 -0400")

Peter Xu <peterx@redhat.com> writes:

> On Wed, Aug 17, 2022 at 02:41:19AM -0700, Nadav Amit wrote:
>> 4. Having multiple TLB flushing infrastructures makes all of these
>> discussions very complicated and unmaintainable. I need to convince myself
>> in every occasion (including this one) whether calls to
>> flush_tlb_batched_pending() and tlb_flush_pending() are needed or not.
>> 
>> What I would like to have [3] is a single infrastructure that gets a
>> “ticket” (generation when the batching started), the old PTE and the new PTE
>> and checks whether a TLB flush is needed based on the arch behavior and the
>> current TLB generation. If needed, it would update the “ticket” to the new
>> generation. Andy wanted a ring for pending TLB flushes, but I think it is an
>> overkill with more overhead and complexity than needed.
>> 
>> But the current situation in which every TLB flush is a basis for long
>> discussions and prone to bugs is impossible.
>> 
>> I hope it helps. Let me know if you want me to revive the patch-set or other
>> feedback.
>> 
>> [1] https://lore.kernel.org/all/20220711034615.482895-5-21cnbao@gmail.com/
>> [2] https://lore.kernel.org/all/20220718120212.3180-13-namit@vmware.com/
>> [3] https://lore.kernel.org/all/20210131001132.3368247-16-namit@vmware.com/
>
> I need more reading on tlb code and also [3] which looks useful to me.
> It's definitely sad to make tlb flushing so complicated.  It'll be great if
> things can be sorted out someday.
>
> In this specific case, the only way to do safe tlb batching in my mind is:
>
> 	pte_offset_map_lock();
> 	arch_enter_lazy_mmu_mode();
>         // If any pending tlb, do it now
>         if (mm_tlb_flush_pending())
> 		flush_tlb_range(vma, start, end);
>         else
>                 flush_tlb_batched_pending();

I don't think we need the above 4 lines.  Because we will flush TLB
before we access the pages.  Can you find any issue if we don't use the
above 4 lines?

Best Regards,
Huang, Ying

>         loop {
>                 ...
>                 pte = ptep_get_and_clear();
>                 ...
>                 if (pte_present())
>                         unmapped++;
>                 ...
>         }
> 	if (unmapped)
> 		flush_tlb_range(walk->vma, start, end);
> 	arch_leave_lazy_mmu_mode();
> 	pte_unmap_unlock();
>
> I may miss something, but even if not it already doesn't look pretty.
>
> Thanks,


  reply	other threads:[~2022-08-18  6:34 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-16  7:39 Alistair Popple
2022-08-16  7:39 ` [PATCH v2 2/2] selftests/hmm-tests: Add test for dirty bits Alistair Popple
2022-08-16  8:10 ` [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page huang ying
2022-08-16 20:35   ` Peter Xu
2022-08-17  1:49     ` Alistair Popple
2022-08-17  2:45       ` Peter Xu
2022-08-17  5:41         ` Alistair Popple
2022-08-17  7:17           ` Huang, Ying
2022-08-17  9:41             ` Nadav Amit
2022-08-17 19:27               ` Peter Xu
2022-08-18  6:34                 ` Huang, Ying [this message]
2022-08-18 14:44                   ` Peter Xu
2022-08-19  2:51                     ` Huang, Ying
2022-08-24  1:56                       ` Alistair Popple
2022-08-24 20:25                         ` Peter Xu
2022-08-24 20:48                           ` Peter Xu
2022-08-25  0:42                             ` Alistair Popple
2022-08-25  1:24                               ` Alistair Popple
2022-08-25 15:04                                 ` Peter Xu
2022-08-25 22:09                                   ` Alistair Popple
2022-08-25 23:36                                     ` Peter Xu
2022-08-25 14:40                               ` Peter Xu
2022-08-18  5:59               ` Huang, Ying
2022-08-17 19:07           ` Peter Xu
2022-08-17  1:38   ` Alistair Popple

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