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02 Nov 2022 01:03:44 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="634167933" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="634167933" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:03:40 -0700 From: "Huang, Ying" To: Michal Hocko Cc: Bharata B Rao , Aneesh Kumar K V , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrew Morton , Alistair Popple , Dan Williams , Dave Hansen , Davidlohr Bueso , Hesham Almatary , Jagdish Gediya , Johannes Weiner , Jonathan Cameron , Tim Chen , Wei Xu , Yang Shi Subject: Re: [RFC] memory tiering: use small chunk size and more tiers In-Reply-To: (Michal Hocko's message of "Wed, 2 Nov 2022 08:51:37 +0100") References: <578c9b89-10eb-1e23-8868-cdd6685d8d4e@linux.ibm.com> <877d0kk5uf.fsf@yhuang6-desk2.ccr.corp.intel.com> <59291b98-6907-0acf-df11-6d87681027cc@linux.ibm.com> <8735b8jy9k.fsf@yhuang6-desk2.ccr.corp.intel.com> <0d938c9f-c810-b10a-e489-c2b312475c52@amd.com> <87tu3oibyr.fsf@yhuang6-desk2.ccr.corp.intel.com> <07912a0d-eb91-a6ef-2b9d-74593805f29e@amd.com> <87leowepz6.fsf@yhuang6-desk2.ccr.corp.intel.com> <878rkuchpm.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Date: Wed, 02 Nov 2022 16:02:54 +0800 Message-ID: <87bkppbx75.fsf@yhuang6-desk2.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ascii ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1667376227; a=rsa-sha256; cv=none; b=HHSXNFhcqtSjyPg3uTz4KPW4bZTArcnD5hRvAiyWHFCWEo+aCD4f30k3ScZ3MYMQoxxGxr UudqP68xdcfdsKnrln0doafWiiUAPgXm+5VA5IfpDvKgKYc9YbeIGav9Jwyz5DKM2QZRIA 4WkQ+lLFo0F1kIpOa1e2e86e7nxf+a8= ARC-Authentication-Results: i=1; imf22.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=Wi91Ft5O; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf22.hostedemail.com: domain of ying.huang@intel.com designates 134.134.136.100 as permitted sender) smtp.mailfrom=ying.huang@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1667376227; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=xqET12ksu6P2rTeZfUSHUDyO93s21f28gsvl8ZHwDmo=; b=QBdl/Ybem2cyaLIUwifWW3GjHC2WdXytmLTjciL/YrfImfqh8twqTlgIJ8msieRV/19csD VSFGwlnD9jfbsB3Yw9O9HPHjrp1sm39OHyDv/MX0jYQjapYicArwWGfy6uaFLh1exILgLo PvNaA0s4Ns0uwA06VQ4O2rf9CwaUD+I= X-Rspamd-Server: rspam02 X-Rspam-User: Authentication-Results: imf22.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=Wi91Ft5O; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf22.hostedemail.com: domain of ying.huang@intel.com designates 134.134.136.100 as permitted sender) smtp.mailfrom=ying.huang@intel.com X-Stat-Signature: e89ko35h81c7ohqpu7617myunkfm133w X-Rspamd-Queue-Id: A6953C0002 X-HE-Tag: 1667376227-854852 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Michal Hocko writes: > On Wed 02-11-22 08:39:49, Huang, Ying wrote: >> Michal Hocko writes: >> >> > On Mon 31-10-22 09:33:49, Huang, Ying wrote: >> > [...] >> >> In the upstream implementation, 4 tiers are possible below DRAM. That's >> >> enough for now. But in the long run, it may be better to define more. >> >> 100 possible tiers below DRAM may be too extreme. >> > >> > I am just curious. Is any configurations with more than couple of tiers >> > even manageable? I mean applications have been struggling even with >> > regular NUMA systems for years and vast majority of them is largerly >> > NUMA unaware. How are they going to configure for a more complex system >> > when a) there is no resource access control so whatever you aim for >> > might not be available and b) in which situations there is going to be a >> > demand only for subset of tears (GPU memory?) ? >> >> Sorry for confusing. I think that there are only several (less than 10) >> tiers in a system in practice. Yes, here, I suggested to define 100 (10 >> in the later text) POSSIBLE tiers below DRAM. My intention isn't to >> manage a system with tens memory tiers. Instead, my intention is to >> avoid to put 2 memory types into one memory tier by accident via make >> the abstract distance range of each memory tier as small as possible. >> More possible memory tiers, smaller abstract distance range of each >> memory tier. > > TBH I do not really understand how tweaking ranges helps anything. > IIUC drivers are free to assign any abstract distance so they will clash > without any higher level coordination. Yes. That's possible. Each memory tier corresponds to one abstract distance range. The larger the range is, the higher the possibility of clashing is. So I suggest to make the abstract distance range smaller to reduce the possibility of clashing. Best Regards, Huang, Ying