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bh=jNnvrR2BjKDF8vvkxnd42jhKJvqR6iRkuTZBVInPryA=; b=Feu7eyOs+fbf+tvFxCVUawXX8xL2LqzUhXIfcHyCM5nIcGNGLOLjiZJ5f9RZ3WcG7shGEw RrO320feaYeli1DbHgAGEbrWP1qWnY3SN4JaPQEeoyfju0hzKpi2RhQn/m2x1q1xFhNlt8 m61Zkv6O5zmLveGXho4QuC52wtDap39ZMwnGDiiw32iJZ+I3wpMbq5xBDeZpNunK8QPRuj ILPkYCJq8CAZofkirkNDGVe2PqI8TAtqu0fBz1v33KOFNZtBpYinGkS5ZNkG9khXPA1NwX lVrjRmrq1rjtrtmyvU2bIyvvoJ4NI5fq6PSSxY8dR1OR226dCLeRtTM6qgY2Pw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1684227250; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=jNnvrR2BjKDF8vvkxnd42jhKJvqR6iRkuTZBVInPryA=; b=App82dMC2e7pvShqFM6/jGHDFwzncKS6yP+iV2bwmf+RpYlmWV+2TmzFPGJEfPQIkVbd0t LilRQSVRsFPFM+CQ== To: Baoquan He Cc: Uladzislau Rezki , Andrew Morton , linux-mm@kvack.org, Christoph Hellwig , Lorenzo Stoakes , Peter Zijlstra , John Ogness , linux-arm-kernel@lists.infradead.org, Russell King , Mark Rutland , Marc Zyngier Subject: Re: Excessive TLB flush ranges In-Reply-To: References: <87a5y5a6kj.ffs@tglx> <87o7mk93tc.ffs@tglx> Date: Tue, 16 May 2023 10:54:09 +0200 Message-ID: <878rdo8xn2.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-Rspam-User: X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 590AC1C0013 X-Stat-Signature: 9ycr19w7m3wr69653m8js5tb9gg93co3 X-HE-Tag: 1684227252-958861 X-HE-Meta: U2FsdGVkX187ReMNenCQ++r/siZ36z3Q3aj+GlOeLCdEQT99RPhB32MyMovQpqc7V7WQ3wHsGdS5mcSoLf8bFIGP+RAbM2icnmfdiKIkWDcgO7efrNnA6IH6sGsmq8bBSEa97GmYUYK6XskmPnmvLOBqpfyofDzaSm4b6+V7eoYn0qofdSvKeCToZCKXR/g2l4o5vNg6ZaeDVq9UioU6fuZgWK3m4+lEB+UcZVz7YtVE4WBP/MhrXNCEyzTRn/gc1GIqG4Tuj9U1JhR4i9/T8CK7HyuLVD5jMy5hVU0rFJkYrZBaoDbJnwFZqekm3gWTWHQkKD5P4yuTJor5bsk/p5f/Mk9QKPVUSS9MisRPlpSOqNuskuQxtY/F+gemKq0gy6TORQ76f/qRL7YlHiFvYooQZVIoYI7fvAvPqgp1bNWxIWMeq0/mkmMg0usLwLw4DoRK6D1ZpkiiUoCM6cdXFWnTgm/ElTMvL2k9vYaM/tJloYuBpRHLJSoeIOdzim97HQjxLMgs2RHN8nPCrHdviTzvjNmiyFOokDFV/mB2KTYbbheKiz49CRb6kZ0aAeh18kHgvJeCumBqcEu69uVgV0TBF4XJ2+s6jX7F1HDEGnfWjaBs8ynlQiuYOUAAThAE6wn6oly6ND6uxRtTRJebHpenPrUNIqPZAdY0o2oa136Q2lZX+3ZT8rhOwWYprtGRxjlYwmROrnM/1NSY7USoq6SQGY4xMpg3ac3cILwxoxMnXRFfg2x2/wlTRgk05l+zmd6gqJFLLM2VndLarloe7hX1wcrTSfmOQmeLurjt8xrRZ1MJuWIyxrBY/wPKnD1m467PO0sFSdzovJiOPL/qMo/+GLegZPRuKMQde5Gj6knKhqXQtBRIC+4mL4GClL3ofyUM3tGZZjbgscOAEnH5h7LLyOqtg6H7+NvX9GcFTZ79gTJ6bG5XnS1Z+kVxrUCBCGU84gRPq1RaMDTW/R3 xEb1TRXs dDvz2uBj0XhkJywydtJrWb8WofrG2THkpuy0JUgGokXuUQBA= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Tue, May 16 2023 at 16:07, Baoquan He wrote: > On 05/16/23 at 08:40am, Thomas Gleixner wrote: >> On Tue, May 16 2023 at 10:26, Baoquan He wrote: >> > On 05/15/23 at 08:17pm, Uladzislau Rezki wrote: >> >> For systems which lack a full TLB flush and to flush a long range is >> >> a problem(it takes time), probably we can flush VA one by one. Because >> >> currently we calculate a flush range [min:max] and that range includes >> >> the space that might not be mapped at all. Like below: >> > >> > It's fine if we only calculate a flush range of [min:max] with VA. In >> > vm_reset_perms(), it calculates the flush range with the impacted direct >> > mapping range, then merge it with VA's range. That looks really strange >> > and surprising. If the vm->pages[] are got from a lower part of physical >> > memory, the final merged flush will span tremendous range. Wondering why >> > we need merge the direct map range with VA range, then do flush. Not >> > sure if I misunderstand it. >> >> So what happens on this BPF teardown is: >> >> The vfree(8k) ends up flushing 3 entries. The actual vmalloc part (2) and >> one extra which is in the direct map. I haven't verified that yet, but I >> assume it's the alias of one of the vmalloc'ed pages. > > It looks like the reason. As Uladzislau pointed out, ARCH-es may > have full TLB flush, so won't get trouble from the merged flush > in the calculated [min:max] way, e.g arm64 and x86's flush_tlb_kernel_range(). > However, arm32 seems lacking the ability of full TLB flash. ARM has a full flush, but it does not check for that in flush_tlb_kernel_range(). > If agreed, I can make a draft patch to do the flush for direct map and > VA seperately, see if it works. Of course it works. Already done that. But you are missing the point. Look at the examples I provided. The current implementation ends up doing a full flush on x86 just to flush 3 TLB entries. For the very same reason because the flush range (start..end) becomes insanely large due to the direct map and vmalloc parts. But doing indivudual flushes for direct map and vmalloc space is silly too because then it ends up doing two IPIs instead of one. IPIs are expensive and the whole point of coalescing the flushes is to spare IPIs, no? So with my hacked up flush_tlb_kernel_vas() I end up having exactly _one_ IPI which walks the list and flushes the 3 TLB entries. Thanks, tglx