From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53A9BC43603 for ; Tue, 17 Dec 2019 20:07:07 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id ED6BA2072D for ; Tue, 17 Dec 2019 20:07:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ED6BA2072D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=xmission.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 54DC68E00A5; Tue, 17 Dec 2019 15:07:06 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 4FD988E0079; Tue, 17 Dec 2019 15:07:06 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 3C8208E00A5; Tue, 17 Dec 2019 15:07:06 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0065.hostedemail.com [216.40.44.65]) by kanga.kvack.org (Postfix) with ESMTP id 244618E0079 for ; Tue, 17 Dec 2019 15:07:06 -0500 (EST) Received: from smtpin03.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with SMTP id BD9314857 for ; Tue, 17 Dec 2019 20:07:05 +0000 (UTC) X-FDA: 76275717210.03.legs30_20b6108c5bf02 X-HE-Tag: legs30_20b6108c5bf02 X-Filterd-Recvd-Size: 6826 Received: from out01.mta.xmission.com (out01.mta.xmission.com [166.70.13.231]) by imf15.hostedemail.com (Postfix) with ESMTP for ; Tue, 17 Dec 2019 20:07:04 +0000 (UTC) Received: from in01.mta.xmission.com ([166.70.13.51]) by out01.mta.xmission.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ihJ7T-000374-FQ; Tue, 17 Dec 2019 13:06:59 -0700 Received: from ip68-227-160-95.om.om.cox.net ([68.227.160.95] helo=x220.xmission.com) by in01.mta.xmission.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.87) (envelope-from ) id 1ihJ7S-0005Fq-8R; Tue, 17 Dec 2019 13:06:58 -0700 From: ebiederm@xmission.com (Eric W. Biederman) To: Catalin Marinas Cc: Arnd Bergmann , Linux ARM , Will Deacon , Marc Zyngier , Vincenzo Frascino , Szabolcs Nagy , Richard Earnshaw , Kevin Brodsky , Andrey Konovalov , Linux-MM , linux-arch , Al Viro References: <20191211184027.20130-1-catalin.marinas@arm.com> <20191211184027.20130-13-catalin.marinas@arm.com> <87zhfxqu1q.fsf@x220.int.ebiederm.org> <20191217174808.GM5624@arrakis.emea.arm.com> Date: Tue, 17 Dec 2019 14:06:01 -0600 In-Reply-To: <20191217174808.GM5624@arrakis.emea.arm.com> (Catalin Marinas's message of "Tue, 17 Dec 2019 17:48:10 +0000") Message-ID: <877e2ura3a.fsf@x220.int.ebiederm.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-XM-SPF: eid=1ihJ7S-0005Fq-8R;;;mid=<877e2ura3a.fsf@x220.int.ebiederm.org>;;;hst=in01.mta.xmission.com;;;ip=68.227.160.95;;;frm=ebiederm@xmission.com;;;spf=neutral X-XM-AID: U2FsdGVkX1/w53SFcKFMEm6MwInTxOOoRY9pew7qlnM= X-SA-Exim-Connect-IP: 68.227.160.95 X-SA-Exim-Mail-From: ebiederm@xmission.com Subject: Re: [PATCH 12/22] arm64: mte: Add specific SIGSEGV codes X-SA-Exim-Version: 4.2.1 (built Thu, 05 May 2016 13:38:54 -0600) X-SA-Exim-Scanned: Yes (on in01.mta.xmission.com) X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Catalin Marinas writes: > Hi Eric, > > On Thu, Dec 12, 2019 at 12:26:41PM -0600, Eric W. Biederman wrote: >> Arnd Bergmann writes: >> > On Wed, Dec 11, 2019 at 7:40 PM Catalin Marinas wrote: >> >> >> >> From: Vincenzo Frascino >> >> >> >> Add MTE-specific SIGSEGV codes to siginfo.h. >> >> >> >> Note that the for MTE we are reusing the same SPARC ADI codes because >> >> the two functionalities are similar and they cannot coexist on the same >> >> system. >> >> Please Please Please don't do that. >> >> It is actively harmful to have architecture specific si_code values. >> As it makes maintenance much more difficult. >> >> Especially as the si_codes are part of union descrimanator. >> >> If your functionality is identical reuse the numbers otherwise please >> just select the next numbers not yet used. > > It makes sense. > >> We have at least 256 si_codes per signal 2**32 if we really need them so >> there is no need to be reuse numbers. >> >> The practical problem is that architecture specific si_codes start >> turning kernel/signal.c into #ifdef soup, and we loose a lot of >> basic compile coverage because of that. In turn not compiling the code >> leads to bit-rot in all kinds of weird places. > > Fortunately for MTE we don't need to change kernel/signal.c. It's > sufficient to call force_sig_fault() from the arch code with the > corresponding signo, code and fault address. Hooray for force_sig_fault at keeping people honest about which parameters they are passing. So far it looks like it is just BUS_MCEERR_AR, BUS_MCEERR_AO, SEGV_BNDERR, and SEGV_PKUERR that are the really confusing ones, as they go beyond the ordinary force_sig_fault layout. But we really do need the knowledge of how all of the cases are encoded or things can get very confusing. Especially when mixing 32bit and 64bit code. >> p.s. As for coexistence there is always the possibility that one chip >> in a cpu family does supports one thing and another chip in a cpu >> family supports another. So userspace may have to cope with the >> situation even if an individual chip doesn't. >> >> I remember a similar case where sparc had several distinct page table >> formats and we had a single kernel that had to cope with them all. > > We have such fun on ARM as well with the big.LITTLE systems where not > all CPUs support the same features. For example, MTE is only enabled > once all the secondary CPUs have booted and confirmed to have the > feature. Which all makes it possible that the alternative to MTE referenced as ADI might show up in some future ARM chip. Which really makes reusing the numbers a bad idea. Not that I actually recall what any of this functionality actually is, but I can tell when people are setting themselves of for a challenge unnecessarily. Eric