From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30A94C32771 for ; Wed, 17 Aug 2022 01:50:12 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id A08596B0073; Tue, 16 Aug 2022 21:50:11 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 9B70B6B0074; Tue, 16 Aug 2022 21:50:11 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 8572C6B0075; Tue, 16 Aug 2022 21:50:11 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 72B0B6B0073 for ; Tue, 16 Aug 2022 21:50:11 -0400 (EDT) Received: from smtpin16.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id 4E3AEC07C0 for ; Wed, 17 Aug 2022 01:50:11 +0000 (UTC) X-FDA: 79807404222.16.1EF6F5F Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by imf03.hostedemail.com (Postfix) with ESMTP id 3BFF7201C3 for ; Wed, 17 Aug 2022 01:50:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660701010; x=1692237010; h=from:to:cc:subject:references:date:in-reply-to: message-id:mime-version; bh=5Qr/rtXTqV1K9DI6syOE1soqcbcEFdZjo5/Won08Vm0=; b=dZY0E8Hu2P590+rRB0ib2dLf9swwCe1gNagqMKOlyjbx0T/FWLhIt9jp Tw/WA2FiA9mYwffiVhH9G671sgJrZMDfSK1p910r8hf2ju1DXUlQpTMPL /fmZFJsS+oPwDeyE4wpPPFsREFX8N1EeMDORMnQdVmWBfyNiBzkoZGU4g 7R1D7fOhnaO80yA0zpk6e57FkwAR58+sGieRkr9lezp9+53rn+phGC4zJ fyaSOHSi7kkbu4uQGZACC1MdQY4e1FEDkXCCrzpnCNCbh5TCTmI9Xy5zu pg6uOYkIbHtcuSp8ke7vkAeXskxjmZ+2KH8RN9tIfXbhJuQXV7R2tHIlz w==; X-IronPort-AV: E=McAfee;i="6400,9594,10441"; a="354121599" X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="354121599" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2022 18:49:53 -0700 X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="935153839" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2022 18:49:50 -0700 From: "Huang, Ying" To: Nadav Amit Cc: Peter Xu , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Minchan Kim , David Hildenbrand , Andrew Morton , Hugh Dickins , Vlastimil Babka , Andrea Arcangeli , Andi Kleen , "Kirill A . Shutemov" , Alistair Popple Subject: Re: [PATCH v3 5/7] mm: Remember young/dirty bit for page migrations References: <20220809220100.20033-1-peterx@redhat.com> <20220809220100.20033-6-peterx@redhat.com> <87pmh6dwdr.fsf@yhuang6-desk2.ccr.corp.intel.com> <5B21352C-2BE6-4070-BB6B-C1B7A5D4D225@gmail.com> Date: Wed, 17 Aug 2022 09:49:48 +0800 In-Reply-To: <5B21352C-2BE6-4070-BB6B-C1B7A5D4D225@gmail.com> (Nadav Amit's message of "Mon, 15 Aug 2022 13:52:49 -0700") Message-ID: <8735dvd4g3.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=ascii ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1660701011; a=rsa-sha256; cv=none; b=GHghsbUkvLckkzEN9rZrkaIsYAzBHMSv5Rgi9cfumfa+VtSj0cU1oxVuWrvyRbSS/qJ2x0 bWlQnyVHQV156w38unvw4PkjKUWECrYRBE5VoC+CDoncbQS4HMe6xS0h6teBgFSBclloOJ QpnyUlry26g/b9YuTXmXGEsSrbTYYDA= ARC-Authentication-Results: i=1; imf03.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=dZY0E8Hu; spf=pass (imf03.hostedemail.com: domain of ying.huang@intel.com designates 134.134.136.31 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1660701011; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=EMAjoUQS9hoO8V2qvVV2setyjCb9BuWtK/mLhTJPV9g=; b=6f78bCklY19JVuvLsnL0rBaWAe6ZWFOdBFl9dFr8GuqyHeAjsKROhP9vvGoY36iD4alVUg Ujw3N0JVvTcv40zCfnLP3sKvjx+cC0TUnCs4oSxJM8cM0I9GHMePw6VHot1XOrkajUJwp9 O2OZFZL1H8XlVCpShxeOBPFGPi1Q3NU= Authentication-Results: imf03.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=dZY0E8Hu; spf=pass (imf03.hostedemail.com: domain of ying.huang@intel.com designates 134.134.136.31 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com X-Rspam-User: X-Stat-Signature: fmscnw17oosyjwz8k4148hjca45345aw X-Rspamd-Queue-Id: 3BFF7201C3 X-Rspamd-Server: rspam06 X-HE-Tag: 1660701009-694539 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Nadav Amit writes: > On Aug 15, 2022, at 12:18 PM, Peter Xu wrote: > >> On Fri, Aug 12, 2022 at 10:32:48AM +0800, Huang, Ying wrote: >>> Peter Xu writes: >>> >>>> On Tue, Aug 09, 2022 at 06:00:58PM -0400, Peter Xu wrote: >>>>> diff --git a/mm/migrate_device.c b/mm/migrate_device.c >>>>> index 27fb37d65476..699f821b8443 100644 >>>>> --- a/mm/migrate_device.c >>>>> +++ b/mm/migrate_device.c >>>>> @@ -221,6 +221,10 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp, >>>>> else >>>>> entry = make_readable_migration_entry( >>>>> page_to_pfn(page)); >>>>> + if (pte_young(pte)) >>>>> + entry = make_migration_entry_young(entry); >>>>> + if (pte_dirty(pte)) >>>>> + entry = make_migration_entry_dirty(entry); >>>>> swp_pte = swp_entry_to_pte(entry); >>>>> if (pte_present(pte)) { >>>>> if (pte_soft_dirty(pte)) >>>> >>>> This change needs to be wrapped with pte_present() at least.. >>>> >>>> I also just noticed that this change probably won't help anyway because: >>>> >>>> (1) When ram->device, the pte will finally be replaced with a device >>>> private entry, and device private entry does not yet support A/D, it >>>> means A/D will be dropped again, >>>> >>>> (2) When device->ram, we are missing information on either A/D bits, or >>>> even if device private entries start to suport A/D, it's still not >>>> clear whether we should take device read/write into considerations >>>> too on the page A/D bits to be accurate. >>>> >>>> I think I'll probably keep the code there for completeness, but I think it >>>> won't really help much until more things are done. >>> >>> It appears that there are more issues. Between "pte = *ptep" and pte >>> clear, CPU may set A/D bit in PTE, so we may need to update pte when >>> clearing PTE. >> >> Agreed, I didn't see it a huge problem with current code, but it should be >> better in that way. >> >>> And I don't find the TLB is flushed in some cases after PTE is cleared. >> >> I think it's okay to not flush tlb if pte not present. But maybe you're >> talking about something else? > > I think Huang refers to situation in which the PTE is cleared, still not > flushed, and then A/D is being set by the hardware. No. The situation in my mind is PTE with A/D set is cleared, not flushed. Then a parallel mprotect or munmap may cause race conditions. As Alistair pointed out in another thread [1], there is TLB flushing after PTL unlocked. But I think we need to flush TLB before unlock. This has been fixed in Alistair's latest version [2]. [1] https://lore.kernel.org/lkml/87r11gvrx6.fsf@nvdebian.thelocal/ [2] https://lore.kernel.org/lkml/6e77914685ede036c419fa65b6adc27f25a6c3e9.1660635033.git-series.apopple@nvidia.com/ Best Regards, Huang, Ying