From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27860C00144 for ; Fri, 29 Jul 2022 06:25:17 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id B69E38E0001; Fri, 29 Jul 2022 02:25:16 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id B18656B0072; Fri, 29 Jul 2022 02:25:16 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 9E0098E0001; Fri, 29 Jul 2022 02:25:16 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id 900A66B0071 for ; Fri, 29 Jul 2022 02:25:16 -0400 (EDT) Received: from smtpin31.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id 60B77C1059 for ; Fri, 29 Jul 2022 06:25:16 +0000 (UTC) X-FDA: 79739150232.31.9F597D3 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by imf02.hostedemail.com (Postfix) with ESMTP id AE2D88008F for ; Fri, 29 Jul 2022 06:25:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659075915; x=1690611915; h=from:to:cc:subject:references:date:in-reply-to: message-id:mime-version; bh=iAb39NiQRMJo7JQGxri/hlWsnn5atvY2xRJlmiRgfaU=; b=LoEnwEPRnzfo1wLe4wmPAltZ5O0r9dqTE/8qVmXZcMqOQt+vDBTLlzz+ OIoh6VL0POa2kx85fXWxp+dc+4dXG+Cax7X9aCXbSI3w55cqABKWDiXCV MBhm0UFJa9cWxF+WKqjYXKchLSqkpX3uFw+vsJrv5X+OWmB3bBwxVIsQL aIj3v6l2Il10a3NWYU2sjWQ1VBbVu1kwB+FycP6ABRzh8b2/h1jdeUe58 A77NMrryfLmB6nUJpS5uTsmewdfVzLpC6UMhE5sJPBsANu927svk8E6EK j8/YgBBNHDvL5idIU0fV7VOksTlTBj1wr5/Jz6gkPbFv9AcxXeYH9TAHz g==; X-IronPort-AV: E=McAfee;i="6400,9594,10422"; a="288716562" X-IronPort-AV: E=Sophos;i="5.93,200,1654585200"; d="scan'208";a="288716562" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2022 23:25:14 -0700 X-IronPort-AV: E=Sophos;i="5.93,200,1654585200"; d="scan'208";a="551632401" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.239.13.94]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2022 23:25:10 -0700 From: "Huang, Ying" To: "Aneesh Kumar K.V" Cc: linux-mm@kvack.org, akpm@linux-foundation.org, Wei Xu , Yang Shi , Davidlohr Bueso , Tim C Chen , Michal Hocko , Linux Kernel Mailing List , Hesham Almatary , Dave Hansen , Jonathan Cameron , Alistair Popple , Dan Williams , Johannes Weiner , jvgediya.oss@gmail.com, Jagdish Gediya Subject: Re: [PATCH v11 1/8] mm/demotion: Add support for explicit memory tiers References: <20220728190436.858458-1-aneesh.kumar@linux.ibm.com> <20220728190436.858458-2-aneesh.kumar@linux.ibm.com> Date: Fri, 29 Jul 2022 14:25:05 +0800 In-Reply-To: <20220728190436.858458-2-aneesh.kumar@linux.ibm.com> (Aneesh Kumar K. V.'s message of "Fri, 29 Jul 2022 00:34:29 +0530") Message-ID: <871qu4mo5a.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=ascii ARC-Authentication-Results: i=1; imf02.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=LoEnwEPR; spf=pass (imf02.hostedemail.com: domain of ying.huang@intel.com designates 192.55.52.115 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1659075916; a=rsa-sha256; cv=none; b=l9EbOwLnnTBP5o6Yhyzd+laGu9gAS9ID9N+/OJ8vDioYTDCbBHkP/o3jrngSSVXDni7jdO mSkX8JbHlDzqTCi24SlWVsxS3jpaWMTT2DJfw/2Kc/RN/CqeDG4XMXlecy6mBCSn8sbwwg zpqqjZ4QmS7whrh4nuFGNYJj3vU+wOc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1659075916; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=i9FkzhwKFNzYQ11XP+E4JvzndYIst2p92zMnIwdRupM=; b=STHzVr+JHRolBcv/wvCVFhsaMDhHLC1Ini74BdxDB6Y8jK/OG+VIo/j2gM3O0eC3UEv3ly l8qZ4xCIrP/84q2JBYTrbFPduS36j0SrPvi+ON1ky9w7XYR3DJvabLXW58+kUfjJITi3/s qc2P8ovP6hLVmuwf+CCZJMezd7/hboc= X-Stat-Signature: arcw995dxy3iyhtmngafn4xbhwzbqedn X-Rspamd-Queue-Id: AE2D88008F X-Rspam-User: Authentication-Results: imf02.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=LoEnwEPR; spf=pass (imf02.hostedemail.com: domain of ying.huang@intel.com designates 192.55.52.115 as permitted sender) smtp.mailfrom=ying.huang@intel.com; dmarc=pass (policy=none) header.from=intel.com X-Rspamd-Server: rspam02 X-HE-Tag: 1659075915-624718 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: "Aneesh Kumar K.V" writes: > In the current kernel, memory tiers are defined implicitly via a demotion path > relationship between NUMA nodes, which is created during the kernel > initialization and updated when a NUMA node is hot-added or hot-removed. The > current implementation puts all nodes with CPU into the highest tier, and builds > the tier hierarchy tier-by-tier by establishing the per-node demotion targets > based on the distances between nodes. > > This current memory tier kernel implementation needs to be improved for several > important use cases, > > The current tier initialization code always initializes each memory-only NUMA > node into a lower tier. But a memory-only NUMA node may have a high performance > memory device (e.g. a DRAM-backed memory-only node on a virtual machine) that > should be put into a higher tier. > > The current tier hierarchy always puts CPU nodes into the top tier. But on a > system with HBM or GPU devices, the memory-only NUMA nodes mapping these devices > should be in the top tier, and DRAM nodes with CPUs are better to be placed into > the next lower tier. > > With current kernel higher tier node can only be demoted to nodes with shortest > distance on the next lower tier as defined by the demotion path, not any other > node from any lower tier. This strict, demotion order does not work in all use > cases (e.g. some use cases may want to allow cross-socket demotion to another > node in the same demotion tier as a fallback when the preferred demotion node is > out of space), This demotion order is also inconsistent with the page allocation > fallback order when all the nodes in a higher tier are out of space: The page > allocation can fall back to any node from any lower tier, whereas the demotion > order doesn't allow that. > > This patch series address the above by defining memory tiers explicitly. > > Linux kernel presents memory devices as NUMA nodes and each memory device is of > a specific type. The memory type of a device is represented by its abstract > distance. A memory tier corresponds to a range of abstract distance. This allows > for classifying memory devices with a specific performance range into a memory > tier. > > This patch configures the range/chunk size to be 128. The default DRAM > abstract distance is 512. We can have 4 memory tiers below the default DRAM > abstract distance which cover the range 0 - 127, 127 - 255, 256- 383, 384 - 511. > Slower memory devices like persistent memory will have abstract distance below > the default DRAM level and hence will be placed in these 4 lower tiers. For abstract distance, the lower value means higher performance, higher value means lower performance. So the abstract distance of PMEM should be smaller than that of DRAM. > A kernel parameter is provided to override the default memory tier. Forget to delete? Best Regards, Huang, Ying > Link: https://lore.kernel.org/linux-mm/CAAPL-u9Wv+nH1VOZTj=9p9S70Y3Qz3+63EkqncRDdHfubsrjfw@mail.gmail.com > Link: https://lore.kernel.org/linux-mm/7b72ccf4-f4ae-cb4e-f411-74d055482026@linux.ibm.com > > Signed-off-by: Jagdish Gediya > Signed-off-by: Aneesh Kumar K.V > --- > include/linux/memory-tiers.h | 17 ++++++ > mm/Makefile | 1 + > mm/memory-tiers.c | 102 +++++++++++++++++++++++++++++++++++ > 3 files changed, 120 insertions(+) > create mode 100644 include/linux/memory-tiers.h > create mode 100644 mm/memory-tiers.c > > diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h > new file mode 100644 > index 000000000000..8d7884b7a3f0 > --- /dev/null > +++ b/include/linux/memory-tiers.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _LINUX_MEMORY_TIERS_H > +#define _LINUX_MEMORY_TIERS_H > + > +/* > + * Each tier cover a abstrace distance chunk size of 128 > + */ > +#define MEMTIER_CHUNK_BITS 7 > +#define MEMTIER_CHUNK_SIZE (1 << MEMTIER_CHUNK_BITS) > +/* > + * For now let's have 4 memory tier below default DRAM tier. > + */ > +#define MEMTIER_ADISTANCE_DRAM (1 << (MEMTIER_CHUNK_BITS + 2)) > +/* leave one tier below this slow pmem */ > +#define MEMTIER_ADISTANCE_PMEM (1 << MEMTIER_CHUNK_BITS) > + > +#endif /* _LINUX_MEMORY_TIERS_H */ > diff --git a/mm/Makefile b/mm/Makefile > index 6f9ffa968a1a..d30acebc2164 100644 > --- a/mm/Makefile > +++ b/mm/Makefile > @@ -92,6 +92,7 @@ obj-$(CONFIG_KFENCE) += kfence/ > obj-$(CONFIG_FAILSLAB) += failslab.o > obj-$(CONFIG_MEMTEST) += memtest.o > obj-$(CONFIG_MIGRATION) += migrate.o > +obj-$(CONFIG_NUMA) += memory-tiers.o > obj-$(CONFIG_DEVICE_MIGRATION) += migrate_device.o > obj-$(CONFIG_TRANSPARENT_HUGEPAGE) += huge_memory.o khugepaged.o > obj-$(CONFIG_PAGE_COUNTER) += page_counter.o > diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c > new file mode 100644 > index 000000000000..01cfd514c192 > --- /dev/null > +++ b/mm/memory-tiers.c > @@ -0,0 +1,102 @@ > +// SPDX-License-Identifier: GPL-2.0 > +#include > +#include > +#include > +#include > +#include > + > +struct memory_tier { > + /* hierarchy of memory tiers */ > + struct list_head list; > + /* list of all memory types part of this tier */ > + struct list_head memory_types; > + /* > + * start value of abstract distance. memory tier maps > + * an abstract distance range, > + * adistance_start .. adistance_start + MEMTIER_CHUNK_SIZE > + */ > + int adistance_start; > +}; > + > +struct memory_dev_type { > + /* list of memory types that are are part of same tier as this type */ > + struct list_head tier_sibiling; > + /* abstract distance for this specific memory type */ > + int adistance; > + /* Nodes of same abstract distance */ > + nodemask_t nodes; > + struct memory_tier *memtier; > +}; > + > +static DEFINE_MUTEX(memory_tier_lock); > +static LIST_HEAD(memory_tiers); > +struct memory_dev_type *node_memory_types[MAX_NUMNODES]; > +/* > + * For now let's have 4 memory tier below default DRAM tier. > + */ > +static struct memory_dev_type default_dram_type = { > + .adistance = MEMTIER_ADISTANCE_DRAM, > + .tier_sibiling = LIST_HEAD_INIT(default_dram_type.tier_sibiling), > +}; > + > +static struct memory_tier *find_create_memory_tier(struct memory_dev_type *memtype) > +{ > + bool found_slot = false; > + struct memory_tier *memtier, *new_memtier; > + int adistance = memtype->adistance; > + unsigned int memtier_adistance_chunk_size = MEMTIER_CHUNK_SIZE; > + > + lockdep_assert_held_once(&memory_tier_lock); > + > + /* > + * If the memtype is already part of a memory tier, > + * just return that. > + */ > + if (memtype->memtier) > + return memtype->memtier; > + > + adistance = round_down(adistance, memtier_adistance_chunk_size); > + list_for_each_entry(memtier, &memory_tiers, list) { > + if (adistance == memtier->adistance_start) { > + memtype->memtier = memtier; > + list_add(&memtype->tier_sibiling, &memtier->memory_types); > + return memtier; > + } else if (adistance < memtier->adistance_start) { > + found_slot = true; > + break; > + } > + } > + > + new_memtier = kzalloc(sizeof(struct memory_tier), GFP_KERNEL); > + if (!new_memtier) > + return ERR_PTR(-ENOMEM); > + > + new_memtier->adistance_start = adistance; > + INIT_LIST_HEAD(&new_memtier->list); > + INIT_LIST_HEAD(&new_memtier->memory_types); > + if (found_slot) > + list_add_tail(&new_memtier->list, &memtier->list); > + else > + list_add_tail(&new_memtier->list, &memory_tiers); > + memtype->memtier = new_memtier; > + list_add(&memtype->tier_sibiling, &new_memtier->memory_types); > + return new_memtier; > +} > + > +static int __init memory_tier_init(void) > +{ > + struct memory_tier *memtier; > + > + mutex_lock(&memory_tier_lock); > + /* CPU only nodes are not part of memory tiers. */ > + default_dram_type.nodes = node_states[N_MEMORY]; > + > + memtier = find_create_memory_tier(&default_dram_type); > + if (IS_ERR(memtier)) > + panic("%s() failed to register memory tier: %ld\n", > + __func__, PTR_ERR(memtier)); > + mutex_unlock(&memory_tier_lock); > + > + return 0; > +} > +subsys_initcall(memory_tier_init);