From: Alistair Popple <apopple@nvidia.com>
To: Yicong Yang <yangyicong@huawei.com>
Cc: catalin.marinas@arm.com, akpm@linux-foundation.org,
linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org,
21cnbao@gmail.com, yangyicong@hisilicon.com
Subject: Re: [PATCH -mm] arm64: tlbflush: Add some comments for TLB batched flushing
Date: Tue, 01 Aug 2023 11:10:37 +1000 [thread overview]
Message-ID: <871qgnd0qt.fsf@nvdebian.thelocal> (raw)
In-Reply-To: <20230729131448.15531-1-yangyicong@huawei.com>
Yicong Yang <yangyicong@huawei.com> writes:
Thanks! I was reading this code the other day and it took me a while to
figure out what was going on. These comments would have been very
helpful and match my understanding, so:
Reviewed-by: Alistair Popple <apopple@nvidia.com>
> From: Yicong Yang <yangyicong@hisilicon.com>
>
> Add comments for arch_flush_tlb_batched_pending() and
> arch_tlbbatch_flush() to illustrate why only a DSB is
> needed.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> ---
> arch/arm64/include/asm/tlbflush.h | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 3456866c6a1d..2bad230b95b4 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -300,11 +300,26 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b
> __flush_tlb_page_nosync(mm, uaddr);
> }
>
> +/*
> + * If mprotect/munmap/etc occurs during TLB batched flushing, we need to
> + * synchronise all the TLBI issued by a DSB to avoid the race mentioned in
> + * flush_tlb_batched_pending().
> + */
> static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm)
> {
> dsb(ish);
> }
>
> +/*
> + * To support TLB batched flush for multiple pages unmapping, we only send
> + * the TLBI for each page in arch_tlbbatch_add_pending() and wait for the
> + * completion at the end in arch_tlbbatch_flush(). Since we've already issued
> + * TLBI for each page so only a DSB is needed to synchronise its effect on the
> + * other CPUs.
> + *
> + * This will save the time waiting on DSB comparing issuing a TLBI;DSB sequence
> + * for each page.
> + */
> static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
> {
> dsb(ish);
prev parent reply other threads:[~2023-08-01 1:12 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-29 13:14 Yicong Yang
2023-07-31 10:34 ` Catalin Marinas
2023-08-01 1:10 ` Alistair Popple [this message]
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