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[217.140.101.70]) by mx.google.com with ESMTP id m24si1845835edm.148.2019.02.15.02.35.17 for ; Fri, 15 Feb 2019 02:35:17 -0800 (PST) Received-SPF: pass (google.com: domain of marc.zyngier@arm.com designates 217.140.101.70 as permitted sender) client-ip=217.140.101.70; Authentication-Results: mx.google.com; spf=pass (google.com: domain of marc.zyngier@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=marc.zyngier@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9A318EBD; Fri, 15 Feb 2019 02:35:16 -0800 (PST) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51D2E3F557; Fri, 15 Feb 2019 02:35:05 -0800 (PST) Date: Fri, 15 Feb 2019 10:34:54 +0000 Message-ID: <865ztls5kh.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Ard Biesheuvel Cc: linux-efi , linux-arm-kernel , Catalin Marinas , Will Deacon , Andrew Morton , James Morse , Linux-MM Subject: Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table In-Reply-To: References: <20190213132738.10294-1-ard.biesheuvel@linaro.org> <20190213132738.10294-2-ard.biesheuvel@linaro.org> <325ae70b-6520-a186-c65f-8ab29a5be3a5@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Thu, 14 Feb 2019 16:55:28 +0000, Ard Biesheuvel wrote: > > On Thu, 14 Feb 2019 at 16:48, Marc Zyngier wrote: > > > > Hi Ard, > > > > On 13/02/2019 13:27, Ard Biesheuvel wrote: > > > In the irqchip and EFI code, we have what basically amounts to a quirk > > > to work around a peculiarity in the GICv3 architecture, which permits > > > the system memory address of LPI tables to be programmable only once > > > after a CPU reset. This means kexec kernels must use the same memory > > > as the first kernel, and thus ensure that this memory has not been > > > given out for other purposes by the time the ITS init code runs, which > > > is not very early for secondary CPUs. > > > > > > On systems with many CPUs, these reservations could overflow the > > > memblock reservation table, and this was addressed in commit > > > eff896288872 ("efi/arm: Defer persistent reservations until after > > > paging_init()"). However, this turns out to have made things worse, > > > since the allocation of page tables and heap space for the resized > > > memblock reservation table itself may overwrite the regions we are > > > attempting to reserve, which may cause all kinds of corruption, > > > also considering that the ITS will still be poking bits into that > > > memory in response to incoming MSIs. > > > > > > So instead, let's grow the static memblock reservation table on such > > > systems so it can accommodate these reservations at an earlier time. > > > This will permit us to revert the above commit in a subsequent patch. > > > > > > Signed-off-by: Ard Biesheuvel > > > --- > > > arch/arm64/include/asm/memory.h | 11 +++++++++++ > > > include/linux/memblock.h | 3 --- > > > mm/memblock.c | 10 ++++++++-- > > > 3 files changed, 19 insertions(+), 5 deletions(-) > > > > > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > > > index e1ec947e7c0c..7e2b13cdd970 100644 > > > --- a/arch/arm64/include/asm/memory.h > > > +++ b/arch/arm64/include/asm/memory.h > > > @@ -332,6 +332,17 @@ static inline void *phys_to_virt(phys_addr_t x) > > > #define virt_addr_valid(kaddr) \ > > > (_virt_addr_is_linear(kaddr) && _virt_addr_valid(kaddr)) > > > > > > +/* > > > + * Given that the GIC architecture permits ITS implementations that can only be > > > + * configured with a LPI table address once, GICv3 systems with many CPUs may > > > + * end up reserving a lot of different regions after a kexec for their LPI > > > + * tables, as we are forced to reuse the same memory after kexec (and thus > > > + * reserve it persistently with EFI beforehand) > > > + */ > > > +#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS) > > > +#define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + 2 * NR_CPUS) > > > > Since GICv3 has 1 pending table per CPU, plus one global property table, > > can we make this 2 * NR_CPUS + 1? Or is that enough already? > > > > Ah, I misread the code then. That would mean we'll only need 1 extra > slot per CPU. > > So I will change this to > > > > +#define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + NR_CPUS) > > considering that INIT_MEMBLOCK_REGIONS defaults to 128, so that one > global table is already accounted for. Look good to me. Thanks, M. -- Jazz is not dead, it just smell funny.