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From: Samuel Holland <samuel.holland@sifive.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, Alexandre Ghiti <alexghiti@rivosinc.com>
Subject: Re: [PATCH v4 10/12] riscv: mm: Make asid_bits a local variable
Date: Thu, 4 Jan 2024 09:49:17 -0600	[thread overview]
Message-ID: <8341e264-53be-4821-ad9a-145e154aeec3@sifive.com> (raw)
In-Reply-To: <ZZV2hKLKtqjhEdvY@xhacker>

On 2024-01-03 9:00 AM, Jisheng Zhang wrote:
> On Tue, Jan 02, 2024 at 02:00:47PM -0800, Samuel Holland wrote:
>> This variable is only used inside asids_init().
> 
> This is due to patch9, so can be folded into patch9.

I'm not sure what you mean here. Patch 9 does not touch any references to the
asid_bits variable, though it does touch adjacent lines.

>>
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>> (no changes since v1)
>>
>>  arch/riscv/mm/context.c | 3 +--
>>  1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
>> index b5170ac1b742..43a8bc2d5af4 100644
>> --- a/arch/riscv/mm/context.c
>> +++ b/arch/riscv/mm/context.c
>> @@ -20,7 +20,6 @@
>>  
>>  DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
>>  
>> -static unsigned long asid_bits;
>>  static unsigned long num_asids;
>>  
>>  static atomic_long_t current_version;
>> @@ -226,7 +225,7 @@ static inline void set_mm(struct mm_struct *prev,
>>  
>>  static int __init asids_init(void)
>>  {
>> -	unsigned long old;
>> +	unsigned long asid_bits, old;
>>  
>>  	/* Figure-out number of ASID bits in HW */
>>  	old = csr_read(CSR_SATP);
>> -- 
>> 2.42.0
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv



  reply	other threads:[~2024-01-04 15:49 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-02 22:00 [PATCH v4 00/12] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-01-02 22:00 ` [PATCH v4 01/12] riscv: Flush the instruction cache during SMP bringup Samuel Holland
2024-01-04 11:58   ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 02/12] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-01-04 12:09   ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 03/12] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland
2024-01-04 12:15   ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 04/12] riscv: Only send remote fences when some other CPU is online Samuel Holland
2024-01-03 14:57   ` Jisheng Zhang
2024-01-03 15:04     ` Jisheng Zhang
2024-01-04 12:33   ` Alexandre Ghiti
2024-01-04 15:33     ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 05/12] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-01-04 12:36   ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 06/12] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-01-02 22:00 ` [PATCH v4 07/12] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-01-02 22:00 ` [PATCH v4 08/12] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-01-04 12:39   ` Alexandre Ghiti
2024-01-04 15:42     ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 09/12] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-01-04 12:42   ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 10/12] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-01-03 15:00   ` Jisheng Zhang
2024-01-04 15:49     ` Samuel Holland [this message]
2024-01-04 12:47   ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 11/12] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-01-04 12:55   ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 12/12] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-01-03 15:02   ` Jisheng Zhang
2024-01-04 15:50     ` Samuel Holland
2024-01-04 13:01   ` Alexandre Ghiti

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