From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D08D7C3A5A9 for ; Mon, 4 May 2020 14:37:21 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 9749F2078C for ; Mon, 4 May 2020 14:37:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9749F2078C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 09B2E8E001F; Mon, 4 May 2020 10:37:21 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 04BB38E0003; Mon, 4 May 2020 10:37:20 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id EA3168E001F; Mon, 4 May 2020 10:37:20 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0253.hostedemail.com [216.40.44.253]) by kanga.kvack.org (Postfix) with ESMTP id D0BD48E0003 for ; Mon, 4 May 2020 10:37:20 -0400 (EDT) Received: from smtpin18.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id 8B217181AEF21 for ; Mon, 4 May 2020 14:37:20 +0000 (UTC) X-FDA: 76779289440.18.wine53_5d4aca46fa48 X-HE-Tag: wine53_5d4aca46fa48 X-Filterd-Recvd-Size: 3911 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by imf28.hostedemail.com (Postfix) with ESMTP for ; Mon, 4 May 2020 14:37:19 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D6461FB; Mon, 4 May 2020 07:37:17 -0700 (PDT) Received: from [10.37.12.17] (unknown [10.37.12.17]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 543783F305; Mon, 4 May 2020 07:37:04 -0700 (PDT) Subject: Re: [PATCH v6 11/25] iommu/arm-smmu-v3: Share process page tables To: jean-philippe@linaro.org Cc: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-mm@kvack.org, joro@8bytes.org, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, kevin.tian@intel.com, baolu.lu@linux.intel.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, christian.koenig@amd.com, felix.kuehling@amd.com, zhangfei.gao@linaro.org, jgg@ziepe.ca, xuzaibo@huawei.com, fenghua.yu@intel.com, hch@infradead.org References: <20200430143424.2787566-1-jean-philippe@linaro.org> <20200430143424.2787566-12-jean-philippe@linaro.org> <580a915f-f8bf-3b3e-c77d-6d0c2ea4bd02@arm.com> <20200504141137.GA170104@myrica> From: Suzuki K Poulose Message-ID: <82f54362-34f1-2378-49c2-2d87e065e385@arm.com> Date: Mon, 4 May 2020 15:42:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20200504141137.GA170104@myrica> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 05/04/2020 03:11 PM, Jean-Philippe Brucker wrote: > On Thu, Apr 30, 2020 at 04:39:53PM +0100, Suzuki K Poulose wrote: >> On 04/30/2020 03:34 PM, Jean-Philippe Brucker wrote: >>> With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR, >>> MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split >>> into two sets, shared and private. Shared ASIDs correspond to those >>> obtained from the arch ASID allocator, and private ASIDs are used for >>> "classic" map/unmap DMA. >>> >>> Cc: Suzuki K Poulose >>> Signed-off-by: Jean-Philippe Brucker >>> --- >> >>> + >>> + tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - VA_BITS) | >>> + FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) | >>> + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) | >>> + FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) | >>> + CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; >>> + >>> + switch (PAGE_SIZE) { >>> + case SZ_4K: >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K); >>> + break; >>> + case SZ_16K: >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K); >>> + break; >>> + case SZ_64K: >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K); >>> + break; >>> + default: >>> + WARN_ON(1); >>> + ret = -EINVAL; >>> + goto err_free_asid; >>> + } >>> + >>> + reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); >>> + par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT); >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par); >>> + >>> + cd->ttbr = virt_to_phys(mm->pgd); >> >> Does the TTBR follow the same layout as TTBR_ELx for 52bit IPA ? i.e, >> TTBR[5:2] = BADDR[51:48] ? Are you covered for that ? > > Good point, I don't remember checking this. The SMMU TTBR doesn't have the > same layout as the CPU's, and we don't need to swizzle the bits. For the > lower bits, the alignment requirements on the pgd are identical to the > MMU. Ok, if that is the case: Acked-by: Suzuki K Poulose