From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0B8EC433FE for ; Thu, 10 Mar 2022 15:16:38 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 15C5F8D0002; Thu, 10 Mar 2022 10:16:38 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 0E50B8D0001; Thu, 10 Mar 2022 10:16:38 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id EC7598D0002; Thu, 10 Mar 2022 10:16:37 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0009.hostedemail.com [216.40.44.9]) by kanga.kvack.org (Postfix) with ESMTP id D9D858D0001 for ; Thu, 10 Mar 2022 10:16:37 -0500 (EST) Received: from smtpin16.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id 8FA44181958BB for ; Thu, 10 Mar 2022 15:16:37 +0000 (UTC) X-FDA: 79228828434.16.D5F16A8 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by imf17.hostedemail.com (Postfix) with ESMTP id 9A2D340020 for ; Thu, 10 Mar 2022 15:16:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646925396; x=1678461396; h=message-id:date:mime-version:to:cc:references:from: subject:in-reply-to:content-transfer-encoding; bh=newON6Td/5uryxsFhwVOGc46gIaVqhB7PFlNeP0VW6Y=; b=V4Ly1hpZgkd+c2KF59gma5zHFHOV+sihUeOEq71j5SKwtUvB6XjySo4Z WrDvYBl+87IvlLNCQwT/KdGwO3/OqCnlCfrRA6l0c1TnfEQCvdYSQuFks L70AnkRbxvlNPbykjjcM8q95h3yUi8kH0c5AuRhKmHQqf8QyazdAsqwHq Fmvwpyghwf6Q/fPfG5MWuA1CAtqfLbCWw7ZYhHgH0vLsaLYrM803PE2wD wOggAh4X6jG3zyZm1WDqlaXudD/CYWIf1dSK+WqDH+eI91JQ4Lqwis6cx +MVyPeOxym0BEUlGYXqKT+TqyGrta9j66uTSyK/18sKmTgnMFIv0n7G6q Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10281"; a="315993224" X-IronPort-AV: E=Sophos;i="5.90,171,1643702400"; d="scan'208";a="315993224" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 07:16:35 -0800 X-IronPort-AV: E=Sophos;i="5.90,171,1643702400"; d="scan'208";a="688685867" Received: from efrantz-mobl1.amr.corp.intel.com (HELO [10.212.252.101]) ([10.212.252.101]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 07:16:34 -0800 Message-ID: <81b6f618-05bc-f7d0-5461-4c3f0ca42d3f@intel.com> Date: Thu, 10 Mar 2022 07:16:27 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Content-Language: en-US To: Bharata B Rao , linux-kernel@vger.kernel.org Cc: linux-mm@kvack.org, x86@kernel.org, kirill.shutemov@linux.intel.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, catalin.marinas@arm.com, will@kernel.org, shuah@kernel.org, oleg@redhat.com, ananth.narayan@amd.com References: <20220310111545.10852-1-bharata@amd.com> From: Dave Hansen Subject: Re: [RFC PATCH v0 0/6] x86/AMD: Userspace address tagging In-Reply-To: <20220310111545.10852-1-bharata@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspamd-Queue-Id: 9A2D340020 X-Stat-Signature: 7qixdopdpte8twwp3inc9cgjqugapcbi X-Rspam-User: Authentication-Results: imf17.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=V4Ly1hpZ; spf=none (imf17.hostedemail.com: domain of dave.hansen@intel.com has no SPF policy when checking 134.134.136.31) smtp.mailfrom=dave.hansen@intel.com; dmarc=pass (policy=none) header.from=intel.com X-Rspamd-Server: rspam07 X-HE-Tag: 1646925396-744650 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 3/10/22 03:15, Bharata B Rao wrote:> > This patchset builds on that prctl() extension and adds support > for AMD UAI. AMD implementation is kept separate as equivalent > Intel LAM implementation is likely to be different due to different > bit positions and tag width. Please don't keep the implementations separate. We'll have one x86 implementation of address bit masking. Both the Intel and AMD implementations will feed into a shared implementation. Something _like_ the cc_set_mask() interface where both implementations do their detection and then call into common code to say how many bits are being ignored. A good litmus test for this is how many vendor-specific checks there are in common code. If there are a lot of them, it's not a good sign for the design. I'd also highly suggest going over Kirill's patch set in detail. There are things like this: > https://lore.kernel.org/linux-mm/20210205151631.43511-10-kirill.shutemov@linux.intel.com/ which seem pretty sane to me but which are (I think) missing in this set. I don't know if we can get there but, in an ideal world, this would be series with, say 7 patches. Patches 1-5 are generic enabling. Patch 6 is tiny and does detection and enabling for UAI. Patch 7 does the same for LAM. All the patches in the series are acked from LAM and UAI folks.