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27 Oct 2022 00:08:07 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10512"; a="737561555" X-IronPort-AV: E=Sophos;i="5.95,217,1661842800"; d="scan'208";a="737561555" Received: from xiaoyaol-hp-g830.ccr.corp.intel.com (HELO [10.249.175.55]) ([10.249.175.55]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2022 00:08:02 -0700 Message-ID: <80e8111b-76a2-4999-782b-fdd4b9f425fa@intel.com> Date: Thu, 27 Oct 2022 15:08:00 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.4.0 Subject: Re: [PATCH v6 01/21] x86/tdx: Use enum to define page level of TDX supported page sizes To: Kai Huang , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, seanjc@google.com, pbonzini@redhat.com, dave.hansen@intel.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, peterz@infradead.org, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com References: <8a5b40d43f8b993a48b99d6647b16a82b433627c.1666824663.git.kai.huang@intel.com> Content-Language: en-US From: Xiaoyao Li In-Reply-To: <8a5b40d43f8b993a48b99d6647b16a82b433627c.1666824663.git.kai.huang@intel.com> Content-Type: text/plain; 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bh=s2wPdPrzB3rS5lhcaTflF+b8pTPxTzKvSuFinNbKGwY=; b=FbROGi34RomKHJ3vHNFZEsAxtxCZRlsfc7Z9OF7MjKsvO0rzWappvwkujkD8+jGTaOFf3W aOwJSXZR7qf+8tXZDqZRIR6bXQF6K17ejst4yI9CxhU6NzS2cTbcbiwUa82ELgzZnIRucq sj/rMmmH84Q2gFIr47UHzzy9VIOt29M= X-Stat-Signature: p7nawuqiry7ry7qkqmaand4oxb4zp3rg X-Rspamd-Queue-Id: 928FE100006 Authentication-Results: imf05.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=FDHKmx+5; spf=pass (imf05.hostedemail.com: domain of xiaoyao.li@intel.com designates 134.134.136.126 as permitted sender) smtp.mailfrom=xiaoyao.li@intel.com; dmarc=pass (policy=none) header.from=intel.com X-Rspam-User: X-Rspamd-Server: rspam05 X-HE-Tag: 1666854489-825330 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 10/27/2022 7:16 AM, Kai Huang wrote: > TDX supports 4K, 2M and 1G page sizes. When TDX guest accepts one page > via try_accept_one(), it passes the page size level to the TDX module. > Currently try_accept_one() uses hard-coded magic number for that. > > Introduce a new enum type to represent the page level of TDX supported > page sizes to replace the hard-coded values. Both initializing the TDX > module and KVM TDX support will need to use that too. > > Also, currently try_accept_one() uses an open-coded switch statement to > get the TDX page level from the kernel page level. As KVM will also > need to do the same thing, introduce a common helper to convert the > kernel page level to the TDX page level. > > Reviewed-by: Kirill A. Shutemov > Signed-off-by: Kai Huang > --- > arch/x86/coco/tdx/tdx.c | 20 ++++---------------- > arch/x86/include/asm/tdx.h | 33 +++++++++++++++++++++++++++++++++ > 2 files changed, 37 insertions(+), 16 deletions(-) > > diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c > index 928dcf7a20d9..c5ff9647213d 100644 > --- a/arch/x86/coco/tdx/tdx.c > +++ b/arch/x86/coco/tdx/tdx.c > @@ -655,7 +655,6 @@ static bool try_accept_one(phys_addr_t *start, unsigned long len, > { > unsigned long accept_size = page_level_size(pg_level); > u64 tdcall_rcx; > - u8 page_size; > > if (!IS_ALIGNED(*start, accept_size)) > return false; > @@ -663,27 +662,16 @@ static bool try_accept_one(phys_addr_t *start, unsigned long len, > if (len < accept_size) > return false; > > + /* TDX only supports 4K/2M/1G page sizes */ yes, a page can be mapped as 1G size to TD via secure/shared EPT. But for this particular TDX_ACCEPT_PAGE case, it only supports 4K and 2M currently, which is defined in TDX module spec. This also implies one thing can be improved in current kernel that trying accepting a page from 1G in tdx_enc_status_changed() can be optimized to from 2M. It can be changed to start from 1G when TDX supports accepting 1G page directly. > + if (pg_level < PG_LEVEL_4K || pg_level > PG_LEVEL_1G) > + return false; > /* > * Pass the page physical address to the TDX module to accept the > * pending, private page. > * > * Bits 2:0 of RCX encode page size: 0 - 4K, 1 - 2M, 2 - 1G. Maybe the “page size” can be adjusted to “TDX page level” accordingly. > */ > - switch (pg_level) { > - case PG_LEVEL_4K: > - page_size = 0; > - break; > - case PG_LEVEL_2M: > - page_size = 1; > - break; > - case PG_LEVEL_1G: > - page_size = 2; > - break; > - default: > - return false; > - } > - > - tdcall_rcx = *start | page_size; > + tdcall_rcx = *start | to_tdx_pg_level(pg_level); > if (__tdx_module_call(TDX_ACCEPT_PAGE, tdcall_rcx, 0, 0, 0, NULL)) > return false; > > diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h > index 020c81a7c729..1c166fb9c22f 100644 > --- a/arch/x86/include/asm/tdx.h > +++ b/arch/x86/include/asm/tdx.h > @@ -20,6 +20,39 @@ > > #ifndef __ASSEMBLY__ > > +#include > + > +/* > + * The page levels of TDX supported page sizes (4K/2M/1G). > + * > + * Those values are part of the TDX module ABI. Do not change them. > + */ > +enum tdx_pg_level { > + TDX_PG_LEVEL_4K, > + TDX_PG_LEVEL_2M, > + TDX_PG_LEVEL_1G, > + TDX_PG_LEVEL_NUM > +}; > + > +/* > + * Get the TDX page level based on the kernel page level. The caller > + * to make sure only pass 4K/2M/1G kernel page level. > + */ > +static inline enum tdx_pg_level to_tdx_pg_level(enum pg_level pglvl) > +{ > + switch (pglvl) { > + case PG_LEVEL_4K: > + return TDX_PG_LEVEL_4K; > + case PG_LEVEL_2M: > + return TDX_PG_LEVEL_2M; > + case PG_LEVEL_1G: > + return TDX_PG_LEVEL_1G; > + default: > + WARN_ON_ONCE(1); > + } > + return TDX_PG_LEVEL_NUM; > +} > + > /* > * Used to gather the output registers values of the TDCALL and SEAMCALL > * instructions when requesting services from the TDX module.