linux-mm.kvack.org archive mirror
 help / color / mirror / Atom feed
From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Kai Huang <kai.huang@intel.com>,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: linux-mm@kvack.org, seanjc@google.com, pbonzini@redhat.com,
	dave.hansen@intel.com, dan.j.williams@intel.com,
	rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com,
	reinette.chatre@intel.com, len.brown@intel.com,
	tony.luck@intel.com, peterz@infradead.org, ak@linux.intel.com,
	isaku.yamahata@intel.com, chao.gao@intel.com,
	sathyanarayanan.kuppuswamy@linux.intel.com, bagasdotme@gmail.com,
	sagis@google.com, imammedo@redhat.com
Subject: Re: [PATCH v6 01/21] x86/tdx: Use enum to define page level of TDX supported page sizes
Date: Thu, 27 Oct 2022 15:08:00 +0800	[thread overview]
Message-ID: <80e8111b-76a2-4999-782b-fdd4b9f425fa@intel.com> (raw)
In-Reply-To: <8a5b40d43f8b993a48b99d6647b16a82b433627c.1666824663.git.kai.huang@intel.com>

On 10/27/2022 7:16 AM, Kai Huang wrote:
> TDX supports 4K, 2M and 1G page sizes.  When TDX guest accepts one page
> via try_accept_one(), it passes the page size level to the TDX module.
> Currently try_accept_one() uses hard-coded magic number for that.
> 
> Introduce a new enum type to represent the page level of TDX supported
> page sizes to replace the hard-coded values.  Both initializing the TDX
> module and KVM TDX support will need to use that too.
> 
> Also, currently try_accept_one() uses an open-coded switch statement to
> get the TDX page level from the kernel page level.  As KVM will also
> need to do the same thing, introduce a common helper to convert the
> kernel page level to the TDX page level.
> 
> Reviewed-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> Signed-off-by: Kai Huang <kai.huang@intel.com>
> ---
>   arch/x86/coco/tdx/tdx.c    | 20 ++++----------------
>   arch/x86/include/asm/tdx.h | 33 +++++++++++++++++++++++++++++++++
>   2 files changed, 37 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
> index 928dcf7a20d9..c5ff9647213d 100644
> --- a/arch/x86/coco/tdx/tdx.c
> +++ b/arch/x86/coco/tdx/tdx.c
> @@ -655,7 +655,6 @@ static bool try_accept_one(phys_addr_t *start, unsigned long len,
>   {
>   	unsigned long accept_size = page_level_size(pg_level);
>   	u64 tdcall_rcx;
> -	u8 page_size;
>   
>   	if (!IS_ALIGNED(*start, accept_size))
>   		return false;
> @@ -663,27 +662,16 @@ static bool try_accept_one(phys_addr_t *start, unsigned long len,
>   	if (len < accept_size)
>   		return false;
>   
> +	/* TDX only supports 4K/2M/1G page sizes */

yes, a page can be mapped as 1G size to TD via secure/shared EPT. But 
for this particular TDX_ACCEPT_PAGE case, it only supports 4K and 2M 
currently, which is defined in TDX module spec.

This also implies one thing can be improved in current kernel that 
trying accepting a page from 1G in tdx_enc_status_changed() can be 
optimized to from 2M. It can be changed to start from 1G when TDX 
supports accepting 1G page directly.

> +	if (pg_level < PG_LEVEL_4K || pg_level > PG_LEVEL_1G)
> +		return false;
>   	/*
>   	 * Pass the page physical address to the TDX module to accept the
>   	 * pending, private page.
>   	 *
>   	 * Bits 2:0 of RCX encode page size: 0 - 4K, 1 - 2M, 2 - 1G.

Maybe the “page size” can be adjusted to “TDX page level” accordingly.

>   	 */
> -	switch (pg_level) {
> -	case PG_LEVEL_4K:
> -		page_size = 0;
> -		break;
> -	case PG_LEVEL_2M:
> -		page_size = 1;
> -		break;
> -	case PG_LEVEL_1G:
> -		page_size = 2;
> -		break;
> -	default:
> -		return false;
> -	}
> -
> -	tdcall_rcx = *start | page_size;
> +	tdcall_rcx = *start | to_tdx_pg_level(pg_level);
>   	if (__tdx_module_call(TDX_ACCEPT_PAGE, tdcall_rcx, 0, 0, 0, NULL))
>   		return false;
>   
> diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h
> index 020c81a7c729..1c166fb9c22f 100644
> --- a/arch/x86/include/asm/tdx.h
> +++ b/arch/x86/include/asm/tdx.h
> @@ -20,6 +20,39 @@
>   
>   #ifndef __ASSEMBLY__
>   
> +#include <asm/pgtable_types.h>
> +
> +/*
> + * The page levels of TDX supported page sizes (4K/2M/1G).
> + *
> + * Those values are part of the TDX module ABI.  Do not change them.
> + */
> +enum tdx_pg_level {
> +	TDX_PG_LEVEL_4K,
> +	TDX_PG_LEVEL_2M,
> +	TDX_PG_LEVEL_1G,
> +	TDX_PG_LEVEL_NUM
> +};
> +
> +/*
> + * Get the TDX page level based on the kernel page level.  The caller
> + * to make sure only pass 4K/2M/1G kernel page level.
> + */
> +static inline enum tdx_pg_level to_tdx_pg_level(enum pg_level pglvl)
> +{
> +	switch (pglvl) {
> +	case PG_LEVEL_4K:
> +		return TDX_PG_LEVEL_4K;
> +	case PG_LEVEL_2M:
> +		return TDX_PG_LEVEL_2M;
> +	case PG_LEVEL_1G:
> +		return TDX_PG_LEVEL_1G;
> +	default:
> +		WARN_ON_ONCE(1);
> +	}
> +	return TDX_PG_LEVEL_NUM;
> +}
> +
>   /*
>    * Used to gather the output registers values of the TDCALL and SEAMCALL
>    * instructions when requesting services from the TDX module.



  reply	other threads:[~2022-10-27  7:08 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-26 23:15 [PATCH v6 00/21] TDX host kernel support Kai Huang
2022-10-26 23:16 ` [PATCH v6 01/21] x86/tdx: Use enum to define page level of TDX supported page sizes Kai Huang
2022-10-27  7:08   ` Xiaoyao Li [this message]
2022-10-27  8:42     ` Huang, Kai
2022-10-27 13:51       ` Kirill A. Shutemov
2022-10-28  0:47         ` Huang, Kai
2022-10-27 22:28       ` Isaku Yamahata
2022-10-27 15:27   ` Dave Hansen
2022-10-28  0:10     ` Huang, Kai
2022-10-26 23:16 ` [PATCH v6 02/21] x86/virt/tdx: Detect TDX during kernel boot Kai Huang
2022-10-26 23:16 ` [PATCH v6 03/21] x86/virt/tdx: Disable TDX if X2APIC is not enabled Kai Huang
2022-10-26 23:16 ` [PATCH v6 04/21] x86/virt/tdx: Use all boot-time system memory as TDX memory Kai Huang
2022-10-26 23:16 ` [PATCH v6 05/21] x86/virt/tdx: Add skeleton to initialize TDX on demand Kai Huang
2022-10-26 23:16 ` [PATCH v6 06/21] x86/virt/tdx: Implement functions to make SEAMCALL Kai Huang
2022-10-26 23:16 ` [PATCH v6 07/21] x86/virt/tdx: Shut down TDX module in case of error Kai Huang
2022-10-26 23:16 ` [PATCH v6 08/21] x86/virt/tdx: Do TDX module global initialization Kai Huang
2022-10-26 23:16 ` [PATCH v6 09/21] x86/virt/tdx: Do logical-cpu scope TDX module initialization Kai Huang
2022-10-26 23:16 ` [PATCH v6 10/21] x86/virt/tdx: Get information about TDX module and TDX-capable memory Kai Huang
2022-10-26 23:16 ` [PATCH v6 11/21] x86/virt/tdx: Sanity check all TDX memory ranges are convertible memory Kai Huang
2022-10-26 23:16 ` [PATCH v6 12/21] x86/virt/tdx: Add placeholder to construct TDMRs to cover all TDX memory regions Kai Huang
2022-10-27 15:31   ` Andi Kleen
2022-10-28  2:21     ` Huang, Kai
2022-11-03  8:55       ` Huang, Kai
2022-11-03 15:05     ` Dave Hansen
2022-11-03 22:07       ` Huang, Kai
2022-10-26 23:16 ` [PATCH v6 13/21] x86/virt/tdx: Create " Kai Huang
2022-10-26 23:16 ` [PATCH v6 14/21] x86/virt/tdx: Allocate and set up PAMTs for TDMRs Kai Huang
2022-10-26 23:16 ` [PATCH v6 15/21] x86/virt/tdx: Set up reserved areas for all TDMRs Kai Huang
2022-10-26 23:16 ` [PATCH v6 16/21] x86/virt/tdx: Reserve TDX module global KeyID Kai Huang
2022-10-27 12:40   ` Andi Kleen
2022-10-28  1:24     ` Huang, Kai
2022-10-26 23:16 ` [PATCH v6 17/21] x86/virt/tdx: Configure TDX module with TDMRs and " Kai Huang
2022-10-26 23:16 ` [PATCH v6 18/21] x86/virt/tdx: Configure global KeyID on all packages Kai Huang
2022-10-27 12:35   ` Andi Kleen
2022-10-28  1:07     ` Huang, Kai
2022-10-26 23:16 ` [PATCH v6 19/21] x86/virt/tdx: Initialize all TDMRs Kai Huang
2022-10-27 12:30   ` Andi Kleen
2022-10-28  1:08     ` Huang, Kai
2022-10-26 23:16 ` [PATCH v6 20/21] x86/virt/tdx: Flush cache in kexec() when TDX is enabled Kai Huang
2022-10-26 23:16 ` [PATCH v6 21/21] Documentation/x86: Add documentation for TDX host support Kai Huang
2022-10-27 12:38   ` Andi Kleen
2022-10-28  2:31     ` Huang, Kai
2022-10-28 12:52   ` Bagas Sanjaya
2022-10-28 14:16     ` Dave Hansen
2022-10-26 23:26 ` [PATCH v6 00/21] TDX host kernel support Dave Hansen
2022-10-26 23:51   ` Huang, Kai

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=80e8111b-76a2-4999-782b-fdd4b9f425fa@intel.com \
    --to=xiaoyao.li@intel.com \
    --cc=ak@linux.intel.com \
    --cc=bagasdotme@gmail.com \
    --cc=chao.gao@intel.com \
    --cc=dan.j.williams@intel.com \
    --cc=dave.hansen@intel.com \
    --cc=imammedo@redhat.com \
    --cc=isaku.yamahata@intel.com \
    --cc=kai.huang@intel.com \
    --cc=kirill.shutemov@linux.intel.com \
    --cc=kvm@vger.kernel.org \
    --cc=len.brown@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mm@kvack.org \
    --cc=pbonzini@redhat.com \
    --cc=peterz@infradead.org \
    --cc=rafael.j.wysocki@intel.com \
    --cc=reinette.chatre@intel.com \
    --cc=sagis@google.com \
    --cc=sathyanarayanan.kuppuswamy@linux.intel.com \
    --cc=seanjc@google.com \
    --cc=tony.luck@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox