Re: [PATCH v11 05/12] x86/mm: add INVLPGB support code

[Rik van Riel <riel@surriel.com>]

On Fri, 2025-02-14 at 10:22 -0800, Dave Hansen wrote:
> On 2/13/25 08:13, Rik van Riel wrote:
> > Add invlpgb.h with the helper functions and definitions needed to
> > use
> > broadcast TLB invalidation on AMD EPYC 3 and newer CPUs.
> 
> You should also note here that (or if??) all these functions get used
> later in the series.
> 
You made me look, and there was indeed one helper
function that is not being used. I removed it,
and added in the commit message that all the (remaining)
functions are used.


> > +/* Flush addr, including globals, for all PCIDs. */
> > +static inline void invlpgb_flush_addr_nosync(unsigned long addr,
> > u16 nr)
> > +{
> > +	__invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL);
> > +}
> 
> Something about the "nr - 1"'s needs to get mentioned *somewhere*. I
> think the best place is actually in __invlpgb(). Basically make the
> calling convention for __invlpgb() be the _sane_ thing where nr==1
> flushes 1 page. Then do the nr-=1 in __invlpgb() and document why.
> 
> I don't mean to insult the AMD ISA designers here. I might have done
> the
> same thing. But the software to use the instruction ends up looking
> really funky. It would be great to limit the number of places that
> deal
> with the funkiness to exactly 1.
> 
> With those two nits addressed:
> 
> Acked-by: Dave Hansen <dave.hansen@linux.intel.com>

Nits addressed, and the Acked-by header added to the
next version :)

Thank you!

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