From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4AF1C43331 for ; Thu, 26 Mar 2020 06:46:04 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 91C0F206F8 for ; Thu, 26 Mar 2020 06:46:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 91C0F206F8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 454B66B000C; Thu, 26 Mar 2020 02:46:04 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 404126B000D; Thu, 26 Mar 2020 02:46:04 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 3415F6B000E; Thu, 26 Mar 2020 02:46:04 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0142.hostedemail.com [216.40.44.142]) by kanga.kvack.org (Postfix) with ESMTP id 1E2AA6B000C for ; Thu, 26 Mar 2020 02:46:04 -0400 (EDT) Received: from smtpin13.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id 14F47485C for ; Thu, 26 Mar 2020 06:46:04 +0000 (UTC) X-FDA: 76636578648.13.sound14_17c7f6aafdc55 X-HE-Tag: sound14_17c7f6aafdc55 X-Filterd-Recvd-Size: 3596 Received: from huawei.com (szxga05-in.huawei.com [45.249.212.191]) by imf09.hostedemail.com (Postfix) with ESMTP for ; Thu, 26 Mar 2020 06:46:03 +0000 (UTC) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id AB80A3012A2B4E7E1AE2; Thu, 26 Mar 2020 14:45:56 +0800 (CST) Received: from [127.0.0.1] (10.173.220.25) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Thu, 26 Mar 2020 14:45:48 +0800 Subject: Re: [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature To: James Morse CC: , , , , , , , , , , , , , , , , , , , , , , , , References: <20200324134534.1570-1-yezhenyu2@huawei.com> From: Zhenyu Ye Message-ID: <7859561b-78b4-4a12-2642-3741d7d3e7b8@huawei.com> Date: Thu, 26 Mar 2020 14:45:46 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi James, On 2020/3/26 0:15, James Morse wrote: > Hi Zhenyu, > > On 3/24/20 1:45 PM, Zhenyu Ye wrote: >> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL >> feature allows TLBs to be issued with a level allowing for quicker >> invalidation. This series provide support for this feature. >> >> Patch 1 and Patch 2 was provided by Marc on his NV series[1] patches, >> which detect the TTL feature and add __tlbi_level interface. > > How does this interact with THP? > (I don't see anything on that in the series.) > > With THP, there is no one answer to the size of mapping in a VMA. > This is a problem because the arm-arm has in "Translation table level > hints" in D5.10.2 of DDI0487E.a: > | If an incorrect value for the entry being invalidated by the > | instruction is specified in the TTL field, then no entries are > | required by the architecture to be invalidated from the TLB. > > If we get it wrong, not TLB maintenance occurs! > Thanks for your review. With THP, we should update the TTL value after the page collapse and merge. If not sure what it should be, we can set it to 0 to avoid "no TLB maintenance occur" problem. The Table D5-53 in DDI0487E.a says: | when TTL[1:0] is 0b00: | This value is reserved, and hardware should treat this as if TTL[3:2] is 0b00 | when TTL[3:2] is 0b00: | Hardware must assume that the entry can be from any level. > Unless THP leaves its fingerprints on the vma, I think you can only do > this for VMA types that THP can't mess with. (see > transparent_hugepage_enabled()) > I will try to add struct mmu_gather to TLBI interfaces, which has enough info to track tlb's level. See in next patch version! Thanks, Zhenyu .