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Tue, 15 Jun 2021 07:19:59 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20210615071959eusmtrp1e135f6e3b85c08046694ef8b87a1a6d5~IsGGsgOEV2144721447eusmtrp1G; Tue, 15 Jun 2021 07:19:59 +0000 (GMT) X-AuditID: cbfec7f4-dd5ff700000024e4-be-60c8549f0815 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 18.10.08696.F9458C06; Tue, 15 Jun 2021 08:19:59 +0100 (BST) Received: from [106.210.134.192] (unknown [106.210.134.192]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20210615071958eusmtip12e3c533f64d669cab1d9e3f5aab42c52~IsGGF7Mdn2836228362eusmtip11; Tue, 15 Jun 2021 07:19:58 +0000 (GMT) Subject: Re: [PATCH 1/1] dma: coherent: check no-map property for arm64 To: Christoph Hellwig , Robin Murphy Cc: Catalin Marinas , Dong Aisheng , Will Deacon , Dong Aisheng , iommu@lists.linux-foundation.org, open list , linux-mm@kvack.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" From: Marek Szyprowski Message-ID: <7729cff3-27b4-c233-7f53-95f6140d3828@samsung.com> Date: Tue, 15 Jun 2021 09:19:57 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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charset="utf-8" X-RootMTR: 20210614153610eucas1p209898b2e8dc013fe6ef072060609c21d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20210614153610eucas1p209898b2e8dc013fe6ef072060609c21d References: <20210611131056.3731084-1-aisheng.dong@nxp.com> <20210614083609.GA18701@willie-the-truck> <20210614145105.GC30667@arm.com> <6f897830-301f-3eb4-785f-de446476e676@arm.com> <20210614153603.GA1998@lst.de> Authentication-Results: imf08.hostedemail.com; dkim=pass header.d=samsung.com header.s=mail20170921 header.b="B//buWfH"; spf=pass (imf08.hostedemail.com: domain of m.szyprowski@samsung.com designates 210.118.77.11 as permitted sender) smtp.mailfrom=m.szyprowski@samsung.com; dmarc=pass (policy=none) header.from=samsung.com X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 2B3E68019357 X-Stat-Signature: 6onuhbthnsp7ub8ztxz5fa7jxw7t5eyb X-HE-Tag: 1623741593-641650 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi Christoph, On 14.06.2021 17:36, Christoph Hellwig wrote: > On Mon, Jun 14, 2021 at 04:34:05PM +0100, Robin Murphy wrote: >>> Looking at the rmem_dma_device_init() -> dma_init_coherent_memory(), it >>> ends up calling memremap(MEMREMAP_WC) which would warn if it intersects >>> with system RAM regardless of the architecture. If the memory region is >>> nomap, it doesn't end up as IORESOURCE_SYSTEM_RAM, so memremap() won't >>> warn. But why is this specific only to arm (or arm64)? >> Didn't some ARMv7 implementations permit unexpected cache hits for the >> non-cacheable address if the same PA has been speculatively fetched via the >> cacheable alias? > If we care about that we need to change these platforms to change the > cache attributes of the kernel direct mapping instead of using vmap. > We already have code to do that for openrisc, someone just needs to > write the glue code for other platforms. ARAIR there is a problem with changing cache attributes of the direct mappings on ARM 32bit. The whole lowmem is mapped with 2M 'section' mappings. Changing cache attributes causes 2 issues. First - one would need to split 2M entry into 4K entries. Second - 2M section mappings for the whole lowmem area are located in the per-process page tables. Changing the cache attributes would require locking all processes and iterating over their page table entries, which is a huge task. Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland