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From: Tom Lendacky <thomas.lendacky@amd.com>
To: Rik van Riel <riel@surriel.com>, Jann Horn <jannh@google.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de,
	peterz@infradead.org, dave.hansen@linux.intel.com,
	zhengqi.arch@bytedance.com, nadav.amit@gmail.com,
	kernel-team@meta.com, linux-mm@kvack.org,
	akpm@linux-foundation.org
Subject: Re: [PATCH v4 04/12] x86/mm: get INVLPGB count max from CPUID
Date: Mon, 13 Jan 2025 16:53:46 -0600	[thread overview]
Message-ID: <73329c7c-0821-df9f-ecf5-880172888513@amd.com> (raw)
In-Reply-To: <bc4f90fb76f82b54069b229291461d5e86a21090.camel@surriel.com>

On 1/13/25 15:08, Rik van Riel wrote:
> On Mon, 2025-01-13 at 16:50 +0100, Jann Horn wrote:
>> On Sun, Jan 12, 2025 at 4:55 PM Rik van Riel <riel@surriel.com>
>> wrote:
>>> +       /* Max number of pages INVLPGB can invalidate in one shot
>>> */
>>> +       if (boot_cpu_has(X86_FEATURE_INVLPGB)) {
>>> +               cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
>>> +               invlpgb_count_max = (edx & 0xffff) + 1;
>>
>> I assume the +1 is just a weird undocumented (or weirdly documented)
>> encoding?
>> https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf
>> says that field InvlpgbCountMax contains the "Maximum page count for
>> INVLPGB instruction" and doesn't mention having to add 1 from what I
>> can tell.
>>
> The way I read the documentation, the number
> passed in to invlpgb (and retrieved from cpuid)
> corresponds to the number of extra pages
> invalidated beyond the first page at the specified
> address.
> 
> Things have not exploded on me invalidating
> multiple pages at once in larger ranges, so I 
> suspect my reading is right, but it would be
> nice for one of the AMD people to confirm :)

That is correct.

Thanks,
Tom
> 


  reply	other threads:[~2025-01-13 22:53 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-12 15:53 [RFC PATCH v4 00/10] AMD broadcast TLB invalidation Rik van Riel
2025-01-12 15:53 ` [PATCH v4 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-14 12:32   ` Borislav Petkov
2025-01-12 15:53 ` [PATCH v4 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-12 15:53 ` [PATCH v4 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-12 15:53 ` [PATCH v4 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-13 15:50   ` Jann Horn
2025-01-13 21:08     ` Rik van Riel
2025-01-13 22:53       ` Tom Lendacky [this message]
2025-01-12 15:53 ` [PATCH v4 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-13 14:21   ` Tom Lendacky
2025-01-13 21:10     ` Rik van Riel
2025-01-14 14:29       ` Tom Lendacky
2025-01-14 15:05         ` Dave Hansen
2025-01-14 15:23           ` Tom Lendacky
2025-01-14 15:47             ` Rik van Riel
2025-01-14 16:30               ` Tom Lendacky
2025-01-14 16:41                 ` Dave Hansen
2025-01-13 17:24   ` Jann Horn
2025-01-14  1:33     ` Rik van Riel
2025-01-14 18:24   ` Michael Kelley
2025-01-12 15:53 ` [PATCH v4 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-12 15:53 ` [PATCH v4 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-12 15:53 ` [PATCH v4 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-12 15:53 ` [PATCH v4 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-13 13:09   ` Nadav Amit
2025-01-14  3:13     ` Rik van Riel
2025-01-12 15:53 ` [PATCH v4 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-13 17:05   ` Jann Horn
2025-01-13 17:48     ` Jann Horn
2025-01-13 21:16     ` Rik van Riel
2025-01-12 15:53 ` [PATCH v4 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-13 11:32   ` Andrew Cooper
2025-01-14  1:28     ` Rik van Riel
2025-01-12 15:53 ` [PATCH v4 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-13 17:11   ` Jann Horn

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