From: Rik van Riel <riel@surriel.com>
To: Tom Lendacky <thomas.lendacky@amd.com>, x86@kernel.org
Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org,
dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com,
nadav.amit@gmail.com, kernel-team@meta.com, linux-mm@kvack.org,
akpm@linux-foundation.org, jannh@google.com
Subject: Re: [PATCH v4 05/12] x86/mm: add INVLPGB support code
Date: Mon, 13 Jan 2025 16:10:41 -0500 [thread overview]
Message-ID: <7045d1666ac5722820a43fffa7f2e6fb3c2eb485.camel@surriel.com> (raw)
In-Reply-To: <685632f2-44a4-a7fd-063b-1d426896f297@amd.com>
On Mon, 2025-01-13 at 08:21 -0600, Tom Lendacky wrote:
> On 1/12/25 09:53, Rik van Riel wrote:
> >
> > +static inline void __invlpgb(unsigned long asid, unsigned long
> > pcid, unsigned long addr,
> > + int extra_count, bool pmd_stride,
> > unsigned long flags)
> > +{
> > + u32 edx = (pcid << 16) | asid;
> > + u32 ecx = (pmd_stride << 31);
> > + u64 rax = addr | flags;
> > +
> > + /* Protect against negative numbers. */
> > + extra_count = max(extra_count, 0);
> > + ecx |= extra_count;
>
> A bad ECX value (ECX[15:0] > invlpgb_count_max) will result in a #GP,
> is
> that ok?
The calling code ensures we do not call this code
with more than invlpgb_count_max pages at a time.
Given the choice between "a bug in the calling code
crashes the kernel" and "a bug in the calling code
results in a missed TLB flush", I'm guessing the
crash is probably better.
--
All Rights Reversed.
next prev parent reply other threads:[~2025-01-13 21:12 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-12 15:53 [RFC PATCH v4 00/10] AMD broadcast TLB invalidation Rik van Riel
2025-01-12 15:53 ` [PATCH v4 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-14 12:32 ` Borislav Petkov
2025-01-12 15:53 ` [PATCH v4 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-12 15:53 ` [PATCH v4 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-12 15:53 ` [PATCH v4 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-13 15:50 ` Jann Horn
2025-01-13 21:08 ` Rik van Riel
2025-01-13 22:53 ` Tom Lendacky
2025-01-12 15:53 ` [PATCH v4 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-13 14:21 ` Tom Lendacky
2025-01-13 21:10 ` Rik van Riel [this message]
2025-01-14 14:29 ` Tom Lendacky
2025-01-14 15:05 ` Dave Hansen
2025-01-14 15:23 ` Tom Lendacky
2025-01-14 15:47 ` Rik van Riel
2025-01-14 16:30 ` Tom Lendacky
2025-01-14 16:41 ` Dave Hansen
2025-01-13 17:24 ` Jann Horn
2025-01-14 1:33 ` Rik van Riel
2025-01-14 18:24 ` Michael Kelley
2025-01-12 15:53 ` [PATCH v4 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-12 15:53 ` [PATCH v4 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-12 15:53 ` [PATCH v4 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-12 15:53 ` [PATCH v4 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-13 13:09 ` Nadav Amit
2025-01-14 3:13 ` Rik van Riel
2025-01-12 15:53 ` [PATCH v4 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-13 17:05 ` Jann Horn
2025-01-13 17:48 ` Jann Horn
2025-01-13 21:16 ` Rik van Riel
2025-01-12 15:53 ` [PATCH v4 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-13 11:32 ` Andrew Cooper
2025-01-14 1:28 ` Rik van Riel
2025-01-12 15:53 ` [PATCH v4 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-13 17:11 ` Jann Horn
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