From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8837FC636D4 for ; Wed, 15 Feb 2023 18:30:51 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 1EF626B0078; Wed, 15 Feb 2023 13:30:51 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 19FD96B007B; Wed, 15 Feb 2023 13:30:51 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 040336B007D; Wed, 15 Feb 2023 13:30:50 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id E6C066B0078 for ; Wed, 15 Feb 2023 13:30:50 -0500 (EST) Received: from smtpin03.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay09.hostedemail.com (Postfix) with ESMTP id 5681B81025 for ; Wed, 15 Feb 2023 18:30:50 +0000 (UTC) X-FDA: 80470367460.03.0DDBA01 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2058.outbound.protection.outlook.com [40.107.92.58]) by imf04.hostedemail.com (Postfix) with ESMTP id 3767C4001F for ; Wed, 15 Feb 2023 18:30:46 +0000 (UTC) Authentication-Results: imf04.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=4HBrd4wz; arc=pass ("microsoft.com:s=arcselector9901:i=1"); spf=pass (imf04.hostedemail.com: domain of Christian.Koenig@amd.com designates 40.107.92.58 as permitted sender) smtp.mailfrom=Christian.Koenig@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1676485847; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=MltqT+d5ESd+pFLe08ckZbNOz7j3FwSRdVvpL1+itvI=; b=LmP2jCYZdnYWQPARVxAiSEQ5W7pD2Q5VJ4tZB3CjnSI5zElx2nnFbDLXZD/lDmyFI91juJ 3jAuzSVyy1y96ZJEQT01LSFCHJnGZRMoxTlcxD36bGD35TmvPaRG8lRy1mvLO/0Ce6gI3h g/kc8XX/2t2SEy9Wl8Mg74ysLhQmhF0= ARC-Authentication-Results: i=2; imf04.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=4HBrd4wz; arc=pass ("microsoft.com:s=arcselector9901:i=1"); spf=pass (imf04.hostedemail.com: domain of Christian.Koenig@amd.com designates 40.107.92.58 as permitted sender) smtp.mailfrom=Christian.Koenig@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com ARC-Seal: i=2; s=arc-20220608; d=hostedemail.com; t=1676485847; a=rsa-sha256; cv=pass; b=lSDF2aIgONdAm9XfTyFBcrufgVlVU6wyf0MVTOiiHN6tELim6uOYlVrh733lVryC3jTGg7 ih4qj4qErjK/z4ouNn1HWcegpPt4lrp6RFIj0vVx1dFsSw/zqiLVZ/lNQM7mGOofXmXOdd 9juKb5j+ujVcZYmpEeHZuhkDYfzCUFI= ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DqPtAetQ260o+/keasKjvJ5LKGLYSJkTNcg0hGqx8tEWDDL8r7QOQiZMgM75GLslxMHf0I8XHMD1CDpWUm5enXrWm++0ZEZ45IPVaNmoGCsp6gJBh5bPod/R2q0zKsuZ5MG3YaG9FnYr7tkmUU/FxNzej3MiuOZsmt93YqmgwKrs3INM9VQZ4vw0SMGlVK5qAWAJjUgUWHqusCQGc9QJrdqAGy9xKQw4uEonoubRUBV9ZU6Bvk2z31y82KZOQGrfV+FlH8gauvHn0t0q6P8jqNqqHpUJm6/exOmrSsSwz+oAupPhqvSYDqAtuey/wPhCMoqrRr5mXrCGpMDaWxD5IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MltqT+d5ESd+pFLe08ckZbNOz7j3FwSRdVvpL1+itvI=; b=ZjUSfspaZpbUIREpV8g1E+ZE2EFzypsVjqESLRY5rchZPNAU81QZy5AgQH+KVE0+hhM5GSczWFPIXNtI2RmPFTiByg4xU3/+gr0ikSt9SozqfddXF13PhSHY1haiHz7lrXCLbH/EpvU+efgRlHrdXiCpw2RPWltoK8kxcq4Tk2X82NpZt595/CilnPHmgVXxk6pSBaZN+ENMZwDqiM81peVqTef/P155J9t1QqA53X7a7FN1W25R2MelN+DzgQoAQwsi8SLsTiOGy6aRu4JrOhrVUco8gcvfK5TOTkXo273vCx8sLDRFjkXNV3+HLF1A/3yDseivK0ZwBCRKHQFsAg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MltqT+d5ESd+pFLe08ckZbNOz7j3FwSRdVvpL1+itvI=; b=4HBrd4wz3vcSyXcJeiWHjvyoZ2g4fwXdtZjd32d0WgmOKlWppblOl1VMv0jaeZOHCbTHZeKA8BsNPThjL8GhKq98+8kMlFgD87p4/nmXhpeMBTvlMoueFk3+HBuIR+fiizynr5b8a8uHHtLWXb3WLtbv4VCCbov+asPUOqx4ESs= Received: from BN8PR12MB3587.namprd12.prod.outlook.com (2603:10b6:408:43::13) by SJ1PR12MB6122.namprd12.prod.outlook.com (2603:10b6:a03:45b::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.26; Wed, 15 Feb 2023 18:30:42 +0000 Received: from BN8PR12MB3587.namprd12.prod.outlook.com ([fe80::2e4f:4041:28be:ba7a]) by BN8PR12MB3587.namprd12.prod.outlook.com ([fe80::2e4f:4041:28be:ba7a%6]) with mapi id 15.20.6086.026; Wed, 15 Feb 2023 18:30:42 +0000 Message-ID: <6fdacb84-bca3-0645-0bb9-ba8def5bd514@amd.com> Date: Wed, 15 Feb 2023 19:30:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [RFC PATCH 07/16] drm/ttm: Reduce the number of used allocation orders for TTM pages Content-Language: en-US To: =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= , dri-devel@lists.freedesktop.org Cc: Andrew Morton , "Matthew Wilcox (Oracle)" , Miaohe Lin , David Hildenbrand , Johannes Weiner , Peter Xu , NeilBrown , Daniel Vetter , Dave Airlie , Dave Hansen , Matthew Auld , linux-graphics-maintainer@vmware.com, linux-mm@kvack.org, intel-gfx@lists.freedesktop.org References: <20230215161405.187368-1-thomas.hellstrom@linux.intel.com> <20230215161405.187368-8-thomas.hellstrom@linux.intel.com> <81f935b26890642f48793c7b7c5685e445bfe0f2.camel@linux.intel.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= In-Reply-To: <81f935b26890642f48793c7b7c5685e445bfe0f2.camel@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR0P281CA0109.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a8::9) To BN8PR12MB3587.namprd12.prod.outlook.com (2603:10b6:408:43::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8PR12MB3587:EE_|SJ1PR12MB6122:EE_ X-MS-Office365-Filtering-Correlation-Id: 453ddabc-f0e2-4f43-5132-08db0f82be61 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EZigXq+LA9Gu2pneT1RHN+A49IIfJidYqQcUPckZSeuCP8llWUQ2UHlV0zypihMiuhcRPHyAA8OzzEc6wc4rE0FErBESr8F5MqR+bL65n77alQs4wZTgDdLXvXWLGcmEPT4EjS5PwNXSWtZa8SLCn70XgoRu4DgzDeA2FFlk8DdSAUS+2PypQ0fwOLZsyjd1vZ5j+awLoQMt5HNF0U1PRaGsME3jxEM7QnERaEgGmjWoUSgxSt1xXKwKiaoByZ5WGunQNNGSGJhfgt2pgHtNs8CJv/nD/yWEuagWHO1umV+fJ9kqWQOJrFsA8kJWmWQWn8bRmtyEyZa0PIPqpHiScYkTYuLoUnXiK11rx5elRLyK+E0Km4jbji9UtnUpeAYOSlyex7JGgblifijtWEPJTzQzD+9o/b4K2QYqbyeGzhBHF8jj45iNKC7Drbsyr8DBfR+8pGvCzdz54Ov3b3Zbbg13c1qP7gM+t2HClgwxlVBu2Vi5S6YlTqkv5FE86yCmzKsOt5q5BWpYcAO3xlmcOHF7JKzsZtWpsH+NsYAnyAhZqrdMKUs9d+tUy8sG0lvAMOaYBdkJ1IxIrVh/PeH4bsPqInk5GvZ7xK3wN6vo9kWYQX2zwj0NbugqisWA3al8u/jTBFcDYGDMW7K0PZ7CyvF2H6a/69+AIEM1SNbO44thk9LCvdVLC8MNsekhopSrOUzxJRYdAC4OoudZX1ndZtjfn+fQkABqOq+zjh7FYCs= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN8PR12MB3587.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(376002)(366004)(136003)(396003)(346002)(451199018)(6512007)(36756003)(478600001)(6486002)(6666004)(38100700002)(186003)(6506007)(66476007)(66574015)(83380400001)(54906003)(8936002)(5660300002)(31696002)(2906002)(45080400002)(7416002)(86362001)(2616005)(41300700001)(316002)(66946007)(66556008)(8676002)(4326008)(31686004)(45980500001)(43740500002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?RHdCbW0xUWhkdnkvNDR1WmthWHZ1WFpmVHNFT0R4MDg4dkpxQ0dJTGRVRkRT?= =?utf-8?B?aVFuVmY4cEhoVmJiSmYxZm5IOFZrTXk5RHV1YmtkSmM2MHo1ZkFFaVRjM3hY?= =?utf-8?B?STBXNkh2a3krQ3NkMEVZcEh6dVdxVGdpbUZhbUZiTllpNUZZWnFmSWtxeDEv?= =?utf-8?B?U3psVEZ2a01oYXp2ZFlsdHl1OVBnNXhlbHB6b0VlSThFbEFnbmRqZSs5alBi?= =?utf-8?B?RFVDKzVjL1VlMGQ4V1IweXNTNlhMRVV6Zy9jTHg0bldRdFl3UVgxSHl2bTRa?= =?utf-8?B?MTJaTFVmNkFadkVkNStrQXZiM0Iwejl4VE1yd3ZZSHE1QWczL05rUmcra0sw?= =?utf-8?B?cXp5MnlTRncrQi9mK01qelV3RU1wNXF4QUdpZ0UrQ1BTU3FqWEVzYk1qZDlo?= =?utf-8?B?UEpkKzRtVEE4dFB0d3lJSlpGY0d5WnN4RkJCRlJYeFZjMWtVeXVuQ0dVMTVY?= =?utf-8?B?ZVJIREhodS9ObG4wVjJSeHBoelMrWGlYRFJmUTVKeFQyWEgvTktHV2lpTEhr?= =?utf-8?B?ZkF1WW1iMExSL2JxN0ROdkdsdm9EQVdiQTZNL0twSlZpSDlHYW1zbWJoczVL?= =?utf-8?B?bzdza2lkcUxmV2lURUxpR0dncVZsUDBOYi9OM0p1aEhGUE43Z2lSckF0Nzhk?= =?utf-8?B?eiswdWt4Ni9VU3FZeVVxODVpQXRBMVNWNGtzMENsWXNSdGNvWjNZNkYydkJn?= =?utf-8?B?WTFKaWl1d2NVOTZ1dU5NWjhlait0Ym9wUTYvZ1FsL0VqNHpGUENOY3AySTAx?= =?utf-8?B?RExHdlJtUm9TWFNaOHhoRE5KMk00WFA3RVNUaFFnN3U5U1hxZzdQcjk5VWtl?= =?utf-8?B?SUFqU3hnOGhIb2Z6d0x5KzRwYlBOM1MwN2tHeUN3MTBQSmdSY2RjVTM4b2xD?= =?utf-8?B?R2ZRQ2w4MTJjNUVRMEJXek02aDJvTGZ2ZS9VUGpVV2ljeDRScmFpWkdONE9u?= =?utf-8?B?OE1hejdnYldsU09wMW9CQUZ4YXM5cUFJTWxucFgyc0F5SXREK094bHlLUHhO?= =?utf-8?B?d1VtVzZLNERwOUJPYW5lT3VTdVdqWmd6aUpvOXNOK0JaSzRqeHJrSENvYjNI?= =?utf-8?B?WTdTeWlQT2VERWx4Q1pna2hQZWtheXJrZzYyL2ZzR0FZT0tyQ3lZay91TGRj?= =?utf-8?B?dFF1NlR4MEZKNHV1d0llQXZLQWREM1BlWExEazgzcXpRcHhHNkVmZzFyYUtx?= =?utf-8?B?ZGd3NXoxa0gxME8vQ01MSVZTaGNUNHVRWGFKSGh2Z2ZaakVmbytYQy9kMlNG?= =?utf-8?B?d0xzWXJGZ0UwOFJiQ1FkeEFaSmpOVExkeDNSbjlwVFlPdkI1ZTg3WlR4bXpH?= =?utf-8?B?UzEvQUJBMGpaK05jVUNBaDhidjNKbGhXTVBjOXFQak9SOUtTZ2QxOHNhYUNz?= =?utf-8?B?bDZhWHlTVzVGUVlDcVNrdkJobTMrOXk2R1Q4RVF5cEJGUUFLa1lXekRialFl?= =?utf-8?B?MkxaK2ZIUmZ0emU0NGozYzBBNTBxM2F5cWgrWFVtS25OaDNBYzNkb25NaDFS?= =?utf-8?B?UVRzNHlBN2ZxZ3JaOXdjM2ZWZWt6K0lTb0FJaktrNzd5ME5EU3MrYWNNbEwv?= =?utf-8?B?bWZEODR1MC8zVVNGcFU2NkVTa1A0enRWV1YrOWoxQUttQVBpbmxxbThqODR6?= =?utf-8?B?RUlwS1FmRjZ2dGxNbzNidkJFYk1PQ3hSVWE3TGFIS3dJQmU2SnRocHI5dU13?= =?utf-8?B?bFVpbXpXQng0dXozS0xzK0ZCekxreU5xUXczdTdjWlJWTDc1L2gvdGgrTWxn?= =?utf-8?B?T3ozbkpTQ2VJdzhmNG1DOThPYlB3bllsWDFJdWlOVG5mS2dnLzRYN1lCRy8v?= =?utf-8?B?SlVOSjRST3BQT0QvOU5xOERwdmM5VVQzSTFkZnh2bFJFU1lUZHo0anh0aHJN?= =?utf-8?B?alFXQldXb2VpM0lSdVU0Vi9nT3habDFwTzhZL3RLNmZuZDhnUTdTckFwRlM1?= =?utf-8?B?aStqaTNKY0FLWlNRUnNRSFVIOUZpNVIxdWg1MFpjRjFBZ2VoOWpWTFBjWXBa?= =?utf-8?B?K203bTl3QjFkMTRQRU9Eek40OGkyZkNhQzdjK01wK1dqd2w1Rzl5VkFSajIr?= =?utf-8?B?WGR6dWpSN3Z1UFFodHp4NEIxWm8yejhhcnY4Vm94VlNYTU9iTS9nUEFaVmpE?= =?utf-8?B?Y1d4a2tvOEQyQSs2N2pMRnF2UEdjb3ZYK243UElRUXh5MTJNSWNSQW1qWDNY?= =?utf-8?Q?3JaDJroZEL98s8ivDs4zfg4W+I5fTK2yvUJ+piGA8dC5?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 453ddabc-f0e2-4f43-5132-08db0f82be61 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3587.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2023 18:30:42.0864 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: phgC6lWCabTnLRVvjN9MjkhCpPvPQZUu+0XJxXSDyFZl6DcTnBe8BuLAS4UGdsvU X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6122 X-Rspam-User: X-Rspamd-Server: rspam03 X-Stat-Signature: oj7xr47fnks6xum7ea7ycitfumrymc1e X-Rspamd-Queue-Id: 3767C4001F X-HE-Tag: 1676485846-974664 X-HE-Meta: U2FsdGVkX1/wFO3mFq458xrs+8gLkkLKdU92UMiXNv53xJNdwcoxXyRymvXOjhA5A6LjQvH3/8fxmRrnwI+W2DuA5ca4EobKx69uiPFArYgNR7uxXJdZjT2I1suAktXBG8lVFGkg10F/rXufFA61++3BygVHiOLIB7JBkhqW+5Khiah7JRPTWS/FIp+EXdZGN81/fB1JuVGDrw2svpsQDZus591916bwusDGANCfHWlhBauMM7wiF8jC9MrgAh9DyJni/+UXJmP/GXFVtDg9vnmTkH+K+VcC4qoDtS2OTr6ZIQ4/+y0n3uP8S0Vj5zEcmQZUcfNZbbFVejDi+LonF/qIONQc1blIXND+R8o+M7v9+2Fm/7UskTViL26BxBGNBQC2yjDn3sNf80R64rAFRBKxeCDRlNtYUpS9biMtUMQujsAlHoatk082HpDqaiURLLNtL4bIqPvAeX09aZE8bsCvoM/EzT7ujzti+vwF2+0iKecC/5b+mLxux/4OWrgtdd8RYA5YOpnDQcQKLlaRQzlkwDlWHX973gKUKe1xPWRW0kwROYCvMxzEAEHo+gaeXy8Z0QkuvO8vQHRExJGUVjetuorWyb7nLXQdxOXXvg9FTdgSWn4cm72U3bfRJtuuSM1EYW1VydfKhDeAv/Wd1V3c3O1moD9eWqMYFltlD/wyh1y/bAaKz4b160m0nCfqbdB4NN5qm9k58Iyf8VzFIqNJs1YXwJZMw6NLQ9n9lzJzrtglAIIpGwD8zB50zysShzOn/cwUXaiizGyx7XBf7SyZoB2VnOteKQ4e2+/flK2hG0vuK/GUeF80S6g/jxMv2DqJ7YERKG9zn5c//qzsRPKuSXRyu8B16Mu1HY3M63OTb0+/30GuIomHJLYxgJdQnsDsOrAUYxWtVVDe5rFHc/639foitkp7OzcYh0uaH9oqORvPpV2H666mpb3h9cwrYDak8TrnTIq0u5AA8O6 pms4VvlW 6iDsBlHV+KKGGddINvaA9VG/7Oz+oahDZVp7AGAPPE8cyF0NNHv+q3OR9sqK5d/NU0iLQcYi7+1No6bpFlfo13w63F6EvDHxfkZOHsvMQozdgSCUErgJyo5tcRZkygMAhkYYluHMBRiTThDr95ZIQVYMGSqAd+b/hRciPBjQM8VxGqsz2pkIZwYYQ8Ke/VdW5+lW9uZRwxki4xsKw38pGaTlBQqvhDv/FumGCwM168t4glQ/bmI5plXl/pV6y4p2SdKl8u3eTbKVbsYU= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Am 15.02.23 um 19:12 schrieb Thomas Hellström: > On Wed, 2023-02-15 at 18:42 +0100, Christian König wrote: >> Am 15.02.23 um 17:13 schrieb Thomas Hellström: >>> When swapping out, we will split multi-order pages both in order to >>> move them to the swap-cache and to be able to return memory to the >>> swap cache as soon as possible on a page-by-page basis. >>> By reducing the page max order to the system PMD size, we can be >>> nicer >>> to the system and avoid splitting gigantic pages. >> >>> On top of this we also >>> include the 64K page size in the page sizes tried, since that >>> appears to >>> be a common size for GPU applications. >> Please completely drop that. > You mean the 64K page size, or the whole patch? The 64K page size. This was an invention from Microsoft to standardize GPU handling ~15-20years ago. It turned out to be a complete shipwreck and by now 2MiB and 1GiB pages or just flexible hardware which can handle everything seem to become standard. >> This is just nonsense spilling in from the >> Windows drivers. > Agreed, but IIRC on the last RFC you asked me not to drop the 64K > pages, so that's why they are here. I can remove them if needed. We could keep it if it's in any way beneficial, but I'm pretty sure I must have been drunk to ask for that. > The only reason for keeping them from a performance point of view is > better efficiency on GPUs with 64K page size if not using a coalescing > IOMMU for dma-mapping. Are any of those still produced? As far as I know neither NVidia, Intel nor AMD still assumes that page size in their hardware for quite a while now. Regards, Christian. > > Let me know what you think is best and I'll adjust accordingly. > > /Thomas > > >> Christian. >> >>> Looking forward to when we might be able to swap out PMD size >>> folios >>> without splitting, this will also be a benefit. >>> >>> Signed-off-by: Thomas Hellström >>> --- >>>   drivers/gpu/drm/ttm/ttm_pool.c | 58 ++++++++++++++++++++++++++--- >>> ----- >>>   1 file changed, 45 insertions(+), 13 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/ttm/ttm_pool.c >>> b/drivers/gpu/drm/ttm/ttm_pool.c >>> index 1cc7591a9542..8787fb6a218b 100644 >>> --- a/drivers/gpu/drm/ttm/ttm_pool.c >>> +++ b/drivers/gpu/drm/ttm/ttm_pool.c >>> @@ -31,6 +31,8 @@ >>>    * cause they are rather slow compared to alloc_pages+map. >>>    */ >>> >>> +#define pr_fmt(fmt) "[TTM POOL] " fmt >>> + >>>   #include >>>   #include >>>   #include >>> @@ -47,6 +49,18 @@ >>> >>>   #include "ttm_module.h" >>> >>> +#define TTM_MAX_ORDER (PMD_SHIFT - PAGE_SHIFT) >>> +#define TTM_64K_ORDER (16 - PAGE_SHIFT) >>> +#if (TTM_MAX_ORDER < TTM_64K_ORDER) >>> +#undef TTM_MAX_ORDER >>> +#define TTM_MAX_ORDER TTM_64K_ORDER >>> +#endif >>> +#if ((MAX_ORDER - 1) < TTM_MAX_ORDER) >>> +#undef TTM_MAX_ORDER >>> +#define TTM_MAX_ORDER (MAX_ORDER - 1) >>> +#endif >>> +#define TTM_DIM_ORDER (TTM_MAX_ORDER + 1) >>> + >>>   /** >>>    * struct ttm_pool_dma - Helper object for coherent DMA mappings >>>    * >>> @@ -65,16 +79,18 @@ module_param(page_pool_size, ulong, 0644); >>> >>>   static atomic_long_t allocated_pages; >>> >>> -static struct ttm_pool_type global_write_combined[MAX_ORDER]; >>> -static struct ttm_pool_type global_uncached[MAX_ORDER]; >>> +static struct ttm_pool_type global_write_combined[TTM_DIM_ORDER]; >>> +static struct ttm_pool_type global_uncached[TTM_DIM_ORDER]; >>> >>> -static struct ttm_pool_type >>> global_dma32_write_combined[MAX_ORDER]; >>> -static struct ttm_pool_type global_dma32_uncached[MAX_ORDER]; >>> +static struct ttm_pool_type >>> global_dma32_write_combined[TTM_DIM_ORDER]; >>> +static struct ttm_pool_type global_dma32_uncached[TTM_DIM_ORDER]; >>> >>>   static spinlock_t shrinker_lock; >>>   static struct list_head shrinker_list; >>>   static struct shrinker mm_shrinker; >>> >>> +static unsigned int ttm_pool_orders[] = {TTM_MAX_ORDER, 0, 0}; >>> + >>>   /* Allocate pages of size 1 << order with the given gfp_flags */ >>>   static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, >>> gfp_t gfp_flags, >>>                                         unsigned int order) >>> @@ -400,6 +416,17 @@ static void __ttm_pool_free(struct ttm_pool >>> *pool, struct ttm_tt *tt, >>>         } >>>   } >>> >>> +static unsigned int ttm_pool_select_order(unsigned int order, >>> pgoff_t num_pages) >>> +{ >>> +       unsigned int *cur_order = ttm_pool_orders; >>> + >>> +       order = min_t(unsigned int, __fls(num_pages), order); >>> +       while (order < *cur_order) >>> +               ++cur_order; >>> + >>> +       return *cur_order; >>> +} >>> + >>>   /** >>>    * ttm_pool_alloc - Fill a ttm_tt object >>>    * >>> @@ -439,9 +466,8 @@ int ttm_pool_alloc(struct ttm_pool *pool, >>> struct ttm_tt *tt, >>>         else >>>                 gfp_flags |= GFP_HIGHUSER; >>> >>> -       for (order = min_t(unsigned int, MAX_ORDER - 1, >>> __fls(num_pages)); >>> -            num_pages; >>> -            order = min_t(unsigned int, order, __fls(num_pages))) >>> { >>> +       order = ttm_pool_select_order(ttm_pool_orders[0], >>> num_pages); >>> +       for (; num_pages; order = ttm_pool_select_order(order, >>> num_pages)) { >>>                 struct ttm_pool_type *pt; >>> >>>                 page_caching = tt->caching; >>> @@ -558,7 +584,7 @@ void ttm_pool_init(struct ttm_pool *pool, >>> struct device *dev, >>> >>>         if (use_dma_alloc) { >>>                 for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i) >>> -                       for (j = 0; j < MAX_ORDER; ++j) >>> +                       for (j = 0; j < TTM_DIM_ORDER; ++j) >>>                                 ttm_pool_type_init(&pool- >>>> caching[i].orders[j], >>>                                                    pool, i, j); >>>         } >>> @@ -578,7 +604,7 @@ void ttm_pool_fini(struct ttm_pool *pool) >>> >>>         if (pool->use_dma_alloc) { >>>                 for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i) >>> -                       for (j = 0; j < MAX_ORDER; ++j) >>> +                       for (j = 0; j < TTM_DIM_ORDER; ++j) >>>                                 ttm_pool_type_fini(&pool- >>>> caching[i].orders[j]); >>>         } >>> >>> @@ -632,7 +658,7 @@ static void ttm_pool_debugfs_header(struct >>> seq_file *m) >>>         unsigned int i; >>> >>>         seq_puts(m, "\t "); >>> -       for (i = 0; i < MAX_ORDER; ++i) >>> +       for (i = 0; i < TTM_DIM_ORDER; ++i) >>>                 seq_printf(m, " ---%2u---", i); >>>         seq_puts(m, "\n"); >>>   } >>> @@ -643,7 +669,7 @@ static void ttm_pool_debugfs_orders(struct >>> ttm_pool_type *pt, >>>   { >>>         unsigned int i; >>> >>> -       for (i = 0; i < MAX_ORDER; ++i) >>> +       for (i = 0; i < TTM_DIM_ORDER; ++i) >>>                 seq_printf(m, " %8u", ttm_pool_type_count(&pt[i])); >>>         seq_puts(m, "\n"); >>>   } >>> @@ -749,10 +775,16 @@ int ttm_pool_mgr_init(unsigned long >>> num_pages) >>>         if (!page_pool_size) >>>                 page_pool_size = num_pages; >>> >>> +       if (TTM_64K_ORDER < TTM_MAX_ORDER) >>> +               ttm_pool_orders[1] = TTM_64K_ORDER; >>> + >>> +       pr_debug("Used orders are %u %u %u\n", ttm_pool_orders[0], >>> +                ttm_pool_orders[1], ttm_pool_orders[2]); >>> + >>>         spin_lock_init(&shrinker_lock); >>>         INIT_LIST_HEAD(&shrinker_list); >>> >>> -       for (i = 0; i < MAX_ORDER; ++i) { >>> +       for (i = 0; i < TTM_DIM_ORDER; ++i) { >>>                 ttm_pool_type_init(&global_write_combined[i], NULL, >>>                                    ttm_write_combined, i); >>>                 ttm_pool_type_init(&global_uncached[i], NULL, >>> ttm_uncached, i); >>> @@ -785,7 +817,7 @@ void ttm_pool_mgr_fini(void) >>>   { >>>         unsigned int i; >>> >>> -       for (i = 0; i < MAX_ORDER; ++i) { >>> +       for (i = 0; i < TTM_DIM_ORDER; ++i) { >>>                 ttm_pool_type_fini(&global_write_combined[i]); >>>                 ttm_pool_type_fini(&global_uncached[i]); >>>