From: nifan.cxl@gmail.com
To: shiju.jose@huawei.com
Cc: linux-edac@vger.kernel.org, linux-cxl@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org, bp@alien8.de, tony.luck@intel.com,
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dan.j.williams@intel.com, dave@stgolabs.net,
jonathan.cameron@huawei.com, dave.jiang@intel.com,
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ira.weiny@intel.com, david@redhat.com, Vilas.Sridharan@amd.com,
leo.duran@amd.com, Yazen.Ghannam@amd.com, rientjes@google.com,
jiaqiyan@google.com, Jon.Grimm@amd.com,
dave.hansen@linux.intel.com, naoya.horiguchi@nec.com,
james.morse@arm.com, jthoughton@google.com,
somasundaram.a@hpe.com, erdemaktas@google.com, pgonda@google.com,
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gthelen@google.com, wschwartz@amperecomputing.com,
dferguson@amperecomputing.com, wbs@os.amperecomputing.com,
nifan.cxl@gmail.com, tanxiaofei@huawei.com,
prime.zeng@hisilicon.com, roberto.sassu@huawei.com,
kangkang.shen@futurewei.com, wanghuiqiang@huawei.com,
linuxarm@huawei.com
Subject: Re: [RFC PATCH v9 06/11] cxl/mbox: Add SET_FEATURE mailbox command
Date: Wed, 17 Jul 2024 13:13:34 -0700 [thread overview]
Message-ID: <66982618.050a0220.e9611.19eb@mx.google.com> (raw)
In-Reply-To: <20240716150336.2042-7-shiju.jose@huawei.com>
On Tue, Jul 16, 2024 at 04:03:30PM +0100, shiju.jose@huawei.com wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Add support for SET_FEATURE mailbox command.
>
> CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
> CXL devices supports features with changeable attributes.
> The settings of a feature can be optionally modified using Set Feature
> command.
Add more specific spec reference to the command here: 8.2.9.6.3.
The same suggestions for get supported features and get feature commands.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> ---
> drivers/cxl/core/mbox.c | 71 +++++++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxlmem.h | 33 +++++++++++++++++++
> 2 files changed, 104 insertions(+)
>
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index b1eeed508459..50ecd2bd7372 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1388,6 +1388,77 @@ size_t cxl_get_feature(struct cxl_memdev_state *mds,
> }
> EXPORT_SYMBOL_NS_GPL(cxl_get_feature, CXL);
>
> +/*
> + * FEAT_DATA_MIN_PAYLOAD_SIZE - min extra number of bytes should be
> + * available in the mailbox for storing the actual feature data so that
> + * the feature data transfer would work as expected.
> + */
> +#define FEAT_DATA_MIN_PAYLOAD_SIZE 10
> +int cxl_set_feature(struct cxl_memdev_state *mds,
> + const uuid_t feat_uuid, u8 feat_version,
> + void *feat_data, size_t feat_data_size,
> + u8 feat_flag)
> +{
> + struct cxl_memdev_set_feat_pi {
> + struct cxl_mbox_set_feat_hdr hdr;
> + u8 feat_data[];
> + } __packed;
> + size_t data_in_size, data_sent_size = 0;
> + struct cxl_mbox_cmd mbox_cmd;
> + size_t hdr_size;
> + int rc = 0;
> +
> + struct cxl_memdev_set_feat_pi *pi __free(kfree) =
> + kmalloc(mds->payload_size, GFP_KERNEL);
> + pi->hdr.uuid = feat_uuid;
> + pi->hdr.version = feat_version;
> + feat_flag &= ~CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK;
Although we may not support it yet, should we set bit[3] (saved across reset)
since we already defined CXL_SET_FEAT_FLAG_DATA_SAVED_ACROSS_RESET and
it is not used?
Fan
> + hdr_size = sizeof(pi->hdr);
> + /*
> + * Check minimum mbox payload size is available for
> + * the feature data transfer.
> + */
> + if (hdr_size + FEAT_DATA_MIN_PAYLOAD_SIZE > mds->payload_size)
> + return -ENOMEM;
> +
> + if ((hdr_size + feat_data_size) <= mds->payload_size) {
> + pi->hdr.flags = cpu_to_le32(feat_flag |
> + CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER);
> + data_in_size = feat_data_size;
> + } else {
> + pi->hdr.flags = cpu_to_le32(feat_flag |
> + CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER);
> + data_in_size = mds->payload_size - hdr_size;
> + }
> +
> + do {
> + pi->hdr.offset = cpu_to_le16(data_sent_size);
> + memcpy(pi->feat_data, feat_data + data_sent_size, data_in_size);
> + mbox_cmd = (struct cxl_mbox_cmd) {
> + .opcode = CXL_MBOX_OP_SET_FEATURE,
> + .size_in = hdr_size + data_in_size,
> + .payload_in = pi,
> + };
> + rc = cxl_internal_send_cmd(mds, &mbox_cmd);
> + if (rc < 0)
> + return rc;
> +
> + data_sent_size += data_in_size;
> + if (data_sent_size >= feat_data_size)
> + return 0;
> +
> + if ((feat_data_size - data_sent_size) <= (mds->payload_size - hdr_size)) {
> + data_in_size = feat_data_size - data_sent_size;
> + pi->hdr.flags = cpu_to_le32(feat_flag |
> + CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER);
> + } else {
> + pi->hdr.flags = cpu_to_le32(feat_flag |
> + CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER);
> + }
> + } while (true);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_set_feature, CXL);
> +
> int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
> struct cxl_region *cxlr)
> {
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 25698a6fbe66..c3cb8e2736b5 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -532,6 +532,7 @@ enum cxl_opcode {
> CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405,
> CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500,
> CXL_MBOX_OP_GET_FEATURE = 0x0501,
> + CXL_MBOX_OP_SET_FEATURE = 0x0502,
> CXL_MBOX_OP_IDENTIFY = 0x4000,
> CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
> CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
> @@ -780,6 +781,34 @@ struct cxl_mbox_get_feat_in {
> u8 selection;
> } __packed;
>
> +/*
> + * Set Feature CXL 3.1 Spec 8.2.9.6.3
> + */
> +
> +/*
> + * Set Feature input payload
> + * CXL rev 3.1 section 8.2.9.6.3 Table 8-101
> + */
> +/* Set Feature : Payload in flags */
> +#define CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK GENMASK(2, 0)
> +enum cxl_set_feat_flag_data_transfer {
> + CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER,
> + CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER,
> + CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER,
> + CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER,
> + CXL_SET_FEAT_FLAG_ABORT_DATA_TRANSFER,
> + CXL_SET_FEAT_FLAG_DATA_TRANSFER_MAX
> +};
> +#define CXL_SET_FEAT_FLAG_DATA_SAVED_ACROSS_RESET BIT(3)
> +
> +struct cxl_mbox_set_feat_hdr {
> + uuid_t uuid;
> + __le32 flags;
> + __le16 offset;
> + u8 version;
> + u8 rsvd[9];
> +} __packed;
> +
> /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
> struct cxl_mbox_poison_in {
> __le64 offset;
> @@ -918,6 +947,10 @@ size_t cxl_get_feature(struct cxl_memdev_state *mds,
> const uuid_t feat_uuid, void *feat_out,
> size_t feat_out_size,
> enum cxl_get_feat_selection selection);
> +int cxl_set_feature(struct cxl_memdev_state *mds,
> + const uuid_t feat_uuid, u8 feat_version,
> + void *feat_data, size_t feat_data_size,
> + u8 feat_flag);
> int cxl_poison_state_init(struct cxl_memdev_state *mds);
> int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
> struct cxl_region *cxlr);
> --
> 2.34.1
>
next prev parent reply other threads:[~2024-07-17 20:14 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-16 15:03 [RFC PATCH v9 00/11] EDAC: Scrub: Introduce generic EDAC RAS control feature driver + CXL/ACPI-RAS2 drivers shiju.jose
2024-07-16 15:03 ` [RFC PATCH v9 01/11] EDAC: Add generic EDAC RAS feature driver shiju.jose
2024-07-16 18:00 ` fan
2024-07-17 11:06 ` Shiju Jose
2024-07-17 10:00 ` Mauro Carvalho Chehab
2024-07-17 11:01 ` Shiju Jose
2024-07-18 6:19 ` Mauro Carvalho Chehab
2024-07-16 15:03 ` [RFC PATCH v9 02/11] EDAC: Add EDAC scrub control driver shiju.jose
2024-07-17 12:56 ` Mauro Carvalho Chehab
2024-07-17 14:07 ` Shiju Jose
2024-07-18 7:03 ` Mauro Carvalho Chehab
2024-07-16 15:03 ` [RFC PATCH v9 03/11] EDAC: Add EDAC ECS " shiju.jose
2024-07-17 13:08 ` Mauro Carvalho Chehab
2024-07-17 17:13 ` nifan.cxl
2024-07-16 15:03 ` [RFC PATCH v9 04/11] cxl/mbox: Add GET_SUPPORTED_FEATURES mailbox command shiju.jose
2024-07-17 17:28 ` nifan.cxl
2024-07-16 15:03 ` [RFC PATCH v9 05/11] cxl/mbox: Add GET_FEATURE " shiju.jose
2024-07-17 18:08 ` nifan.cxl
2024-07-18 9:11 ` Shiju Jose
2024-07-16 15:03 ` [RFC PATCH v9 06/11] cxl/mbox: Add SET_FEATURE " shiju.jose
2024-07-17 20:13 ` nifan.cxl [this message]
2024-07-18 9:15 ` Shiju Jose
2024-07-16 15:03 ` [RFC PATCH v9 07/11] cxl/memscrub: Add CXL memory device patrol scrub control feature shiju.jose
2024-07-18 22:02 ` fan
2024-07-16 15:03 ` [RFC PATCH v9 08/11] cxl/memscrub: Add CXL memory device ECS " shiju.jose
2024-07-19 18:43 ` fan
2024-07-24 9:10 ` Shiju Jose
2024-07-16 15:03 ` [RFC PATCH v9 09/11] platform: Add __free() based cleanup function for platform_device_put shiju.jose
2024-07-16 15:03 ` [RFC PATCH v9 10/11] ACPI:RAS2: Add ACPI RAS2 driver shiju.jose
2024-07-16 15:03 ` [RFC PATCH v9 11/11] ras: scrub: ACPI RAS2: Add memory " shiju.jose
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