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whether the data cache is virtually > aliased on all architectures. Its purpose is to ensure that subsystems > which are incompatible with virtually aliased data caches (e.g. FS_DAX) > can reliably query this. > > For data cache aliasing, there are three scenarios dependending on the > architecture. Here is a breakdown based on my understanding: > > A) The data cache is always aliasing: > > * arc > * csky > * m68k (note: shared memory mappings are incoherent ? SHMLBA is missing there.) > * sh > * parisc > > B) The data cache aliasing is statically known or depends on querying CPU > state at runtime: > > * arm (cache_is_vivt() || cache_is_vipt_aliasing()) > * mips (cpu_has_dc_aliases) > * nios2 (NIOS2_DCACHE_SIZE > PAGE_SIZE) > * sparc32 (vac_cache_size > PAGE_SIZE) > * sparc64 (L1DCACHE_SIZE > PAGE_SIZE) > * xtensa (DCACHE_WAY_SIZE > PAGE_SIZE) > > C) The data cache is never aliasing: > > * alpha > * arm64 (aarch64) > * hexagon > * loongarch (but with incoherent write buffers, which are disabled since > commit d23b7795 ("LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE")) > * microblaze > * openrisc > * powerpc > * riscv > * s390 > * um > * x86 > > Require architectures in A) and B) to select ARCH_HAS_CPU_CACHE_ALIASING and > implement "cpu_dcache_is_aliasing()". > > Architectures in C) don't select ARCH_HAS_CPU_CACHE_ALIASING, and thus > cpu_dcache_is_aliasing() simply evaluates to "false". > > Note that this leaves "cpu_icache_is_aliasing()" to be implemented as future > work. This would be useful to gate features like XIP on architectures > which have aliasing CPU dcache-icache but not CPU dcache-dcache. > > Use "cpu_dcache" and "cpu_cache" rather than just "dcache" and "cache" > to clarify that we really mean "CPU data cache" and "CPU cache" to > eliminate any possible confusion with VFS "dentry cache" and "page > cache". > > Link: https://lore.kernel.org/lkml/20030910210416.GA24258@mail.jlokier.co.uk/ > Fixes: d92576f1167c ("dax: does not work correctly with virtual aliasing caches") > Signed-off-by: Mathieu Desnoyers > Cc: Andrew Morton > Cc: Linus Torvalds > Cc: Dan Williams > Cc: Vishal Verma > Cc: Dave Jiang > Cc: Matthew Wilcox > Cc: Arnd Bergmann > Cc: Russell King > Cc: linux-arch@vger.kernel.org > Cc: linux-cxl@vger.kernel.org > Cc: linux-fsdevel@vger.kernel.org > Cc: linux-mm@kvack.org > Cc: linux-xfs@vger.kernel.org > Cc: dm-devel@lists.linux.dev > Cc: nvdimm@lists.linux.dev > --- > arch/arc/Kconfig | 1 + > arch/arc/include/asm/cachetype.h | 9 +++++++++ > arch/arm/Kconfig | 1 + > arch/arm/include/asm/cachetype.h | 2 ++ > arch/csky/Kconfig | 1 + > arch/csky/include/asm/cachetype.h | 9 +++++++++ > arch/m68k/Kconfig | 1 + > arch/m68k/include/asm/cachetype.h | 9 +++++++++ > arch/mips/Kconfig | 1 + > arch/mips/include/asm/cachetype.h | 9 +++++++++ > arch/nios2/Kconfig | 1 + > arch/nios2/include/asm/cachetype.h | 10 ++++++++++ > arch/parisc/Kconfig | 1 + > arch/parisc/include/asm/cachetype.h | 9 +++++++++ > arch/sh/Kconfig | 1 + > arch/sh/include/asm/cachetype.h | 9 +++++++++ > arch/sparc/Kconfig | 1 + > arch/sparc/include/asm/cachetype.h | 14 ++++++++++++++ > arch/xtensa/Kconfig | 1 + > arch/xtensa/include/asm/cachetype.h | 10 ++++++++++ > include/linux/cacheinfo.h | 6 ++++++ > mm/Kconfig | 6 ++++++ > 22 files changed, 112 insertions(+) > create mode 100644 arch/arc/include/asm/cachetype.h > create mode 100644 arch/csky/include/asm/cachetype.h > create mode 100644 arch/m68k/include/asm/cachetype.h > create mode 100644 arch/mips/include/asm/cachetype.h > create mode 100644 arch/nios2/include/asm/cachetype.h > create mode 100644 arch/parisc/include/asm/cachetype.h > create mode 100644 arch/sh/include/asm/cachetype.h > create mode 100644 arch/sparc/include/asm/cachetype.h > create mode 100644 arch/xtensa/include/asm/cachetype.h > [..] > diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h > index d504eb4b49ab..2cb15fe4fe12 100644 > --- a/include/linux/cacheinfo.h > +++ b/include/linux/cacheinfo.h > @@ -138,4 +138,10 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level) > #define use_arch_cache_info() (false) > #endif > > +#ifndef CONFIG_ARCH_HAS_CPU_CACHE_ALIASING > +#define cpu_dcache_is_aliasing() false > +#else > +#include > +#endif > + > #endif /* _LINUX_CACHEINFO_H */ > diff --git a/mm/Kconfig b/mm/Kconfig > index 57cd378c73d6..db09c9ad15c9 100644 > --- a/mm/Kconfig > +++ b/mm/Kconfig > @@ -1016,6 +1016,12 @@ config IDLE_PAGE_TRACKING > See Documentation/admin-guide/mm/idle_page_tracking.rst for > more details. > > +# Architectures which implement cpu_dcache_is_aliasing() to query > +# whether the data caches are aliased (VIVT or VIPT with dcache > +# aliasing) need to select this. > +config ARCH_HAS_CPU_CACHE_ALIASING > + bool > + > config ARCH_HAS_CACHE_LINE_SIZE > bool I can't speak to the specific arch changes, but the generic support above looks ok. If you get any pushback on the per arch changes then maybe this could be split into a patch that simply does the coarse grained select of CONFIG_ARCH_HAS_CPU_CACHE_ALIASING for ARM, MIPS, and SPARC. Then, follow-on with patches per-arch to do the more fine grained option. Certainly Andrew's tree is great for simultaneous cross arch changes like this.