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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id q24sm3923678wmq.24.2021.02.16.07.59.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Feb 2021 07:59:53 -0800 (PST) To: Peter Zijlstra , Andi Kleen Cc: Joerg Roedel , David Rientjes , Borislav Petkov , Andy Lutomirski , Sean Christopherson , Andrew Morton , "Kirill A. Shutemov" , Brijesh Singh , Tom Lendacky , Jon Grimm , Thomas Gleixner , Christoph Hellwig , Ingo Molnar , x86@kernel.org, linux-mm@kvack.org References: <20210212131907.GI5453@suse.de> <20210212145318.GK5453@suse.de> <20210212152813.GA28884@suse.de> <20210212161849.GB28884@suse.de> <20210216100045.GE28884@suse.de> <20210216142741.GI365765@tassilo.jf.intel.com> From: Paolo Bonzini Subject: Re: AMD SEV-SNP/Intel TDX: validation of memory pages Message-ID: <5ff9690f-331a-8322-3431-212b14f64fcc@redhat.com> Date: Tue, 16 Feb 2021 16:59:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 16/02/21 15:46, Peter Zijlstra wrote: > On Tue, Feb 16, 2021 at 06:27:41AM -0800, Andi Kleen wrote: >> I think the IST solution should at least be explored before >> dismissing it. It might be simpler than anything else (like >> using new APIs) >=20 > Have you seen the trainwreck bonzini proposed? You had been suspiciously silent... > The very simplest thing is saying no to TDX. >=20 > That 'solution' also hard relies on #VE not nesting more than once, so > lovely things like: #VE -> #DB -> #VE -> #NMI -> #VE, or #VE -> NMI -> > #VE -> #MC -> #VE or any number of other possible 'fun' combinations > _must_ not happen. ... but no, this is not how it works. It is actually guaranteed that=20 #VE does not nest more than once, and that's the big difference with NMIs= . Let's look at the first case you listed, this is what would happen: #VE handler starts on stack 1 First #VE processing... clear VE-in-progress flag in the info block (allowing reentrancy) #DB handler starts nested #VE handler starts on stack 2 outer #VE handler marks stack 1 for reexecution nested #VE handler ends *** #DB handler ends #VE handler IRETs back to the start of the handler itself Second #VE processing starts (also on stack 1) clear VE-in-progress flag in the info block #NMI handler nested #VE handler starts on stack 2 outer #VE handler marks stack 1 for reexecution nested #VE handler ends *** #NMI handler ends #VE handler IRETs back to the start of the handler itself Third #VE processing starts (also on stack 1) clear VE-in-progress flag in the info block #VE handler IRETs back to the caller Two things of note: - note that at the points marked *** the nested #VE handler has not=20 allowed another exception to come. That only happens in the outer handle= r. - the inner handler does nothing but telling the outer handler to rerun.=20 The way it does it is certainly not pretty, because it has to work at=20 any instruction boundary, but at its heart it's basically a do{}while loo= p. Paolo > And yes, I know #MC isn't supported just now, but the above would > mandate it never be supported _ever_, because otherwise the IST hack > crumbles. >=20 > Again, repeat after me: ISTs are a part of the problem. >=20 > So how about fixing TDX instead of forcing us to do horrible fragile > things we all know will end up in tears? >=20