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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 719D118000D X-Stat-Signature: jehy7bquhxjqqqzozerkkqwidd7ie4fi X-HE-Tag: 1770795512-997148 X-HE-Meta: U2FsdGVkX1+vNIk8FWJL+IiCQjhGu58IT4pPoqYQKVaLsNe4651PwY1gyBSVNI+RnOcxvzuCHZ5VLuNOlBXy+r2ZSSWJqXmNL4S7X8rFOZm67NqeKg5q+Ueq9YVlPSWkpqOlDazty1iYPw2Yg58gHz08f9aUH9Aa0bdpif4L9eNL5zg3wPTwSFjqHoJq5ZcfHia3X0fU2f8ggIr2bWEHjv7mkpxxZwihcetEdnJ9x4AYdTIDWJ4vFrMU+cekNFWCHYzAplP5xSohUeABk2zZuGWQIz5+mhYrz2qWTZtMEUFXTSArnUU1OUJsnCweFh5ZC6cRtU+f2WFC80HHSn6Nj3bjDec4vl7UTtkIODXKUUglYxUqAcXaVnXarH180AW6FvBA6nc114wIuR8bLEqXxzshFjhvfo1q9vrVlk1VZWvqhVSfsrCSDlbIfbNX4Pgq7Vt7xKNkoV7LX31gEfcREyozwTH/SfJLH9kWgGsuMvtbjK6/moQzzWo6NlnCAk74T363J7RorDk4xNvrqxG3nAOrVohgUo0zpui0uAidy20Iu94vqmyWP3+RAQUNE7QjdND2aDmk7QbXqOTXd/LpWlSBEe+zIs2G/vvIMFdfGoKUrbQiUu8+NTEHv1VeWI9DWZA/3dARM8OJY8Zj7J/CamHUi77wPwN14RckDjyYgnFy7TPCqxpvSxL4jy3G5vXbj2J81hdRaEw2Q0Di1XoSmDgceo6uPzsbZjAkudzOl9MmNPO/M3gXjHFQ2CWXneK284B5VG2attKW7xQ/fYF4n6dP76u1L3tqv8ZdaU8fLKAPvOKEBYRAdCw8RebK4ZNBP8YzlpIFPRVQwDlSEoSQlvXmjdIOzPZYfoYUCFp81Eqn0Xbit8UDDT10BK/wZSKq0vuJe8nT48Y= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On 10/02/26 9:59 pm, Shakeel Butt wrote: > On Tue, Feb 10, 2026 at 01:08:49PM +0530, Dev Jain wrote: > [...] >>> Oh so it is arm64 specific issue. I tested on x86-64 machine and it solves >>> the little regression it had before. So, on arm64 all this_cpu_ops i.e. without >>> double underscore, uses LL/SC instructions. >>> >>> Need more thought on this. >>> >>>>> Also can you confirm whether my analysis of the regression was correct? >>>>> Because if it was, then this diff looks wrong - AFAIU preempt_disable() >>>>> won't stop an irq handler from interrupting the execution, so this >>>>> will introduce a bug for code paths running in irq context. >>>>> >>>> I was worried about the correctness too, but this_cpu_add() is safe >>>> against IRQs and so the stat will be _eventually_ consistent? >>>> >>>> Ofc it's so confusing! Maybe I'm the one confused. >>> Yeah there is no issue with proposed patch as it is making the function >>> re-entrant safe. >> Ah yes, this_cpu_add() does the addition in one shot without read-modify-write. >> >> I am still puzzled whether the original patch was a bug fix or an optimization. > The original patch was a cleanup patch. The memcg stats update functions > were already irq/nmi safe without disabling irqs and that patch did the > same for the numa stats. Though it seems like that is causing regression > for arm64 as this_cpu* ops are expensive on arm64. > >> The patch description says that node stat updation uses irq unsafe interface. >> Therefore, we had foo() calling __foo() nested with local_irq_save/restore. But >> there were code paths which directly called __foo() - so, your patch fixes a bug right > No, those places were already disabling irqs and should be fine. Please correct me if I am missing something here. Simply putting an if (!irqs_disabled()) -> dump_stack() in __lruvec_stat_mod_folio, before calling __mod_node_page_state, reveals: [ 6.486375] Call trace: [ 6.486376] show_stack+0x20/0x38 (C) [ 6.486379] dump_stack_lvl+0x74/0x90 [ 6.486382] dump_stack+0x18/0x28 [ 6.486383] __lruvec_stat_mod_folio+0x160/0x180 [ 6.486385] folio_add_file_rmap_ptes+0x128/0x480 [ 6.486388] set_pte_range+0xe8/0x320 [ 6.486389] finish_fault+0x260/0x508 [ 6.486390] do_fault+0x2d0/0x598 [ 6.486391] __handle_mm_fault+0x398/0xb60 [ 6.486393] handle_mm_fault+0x15c/0x298 [ 6.486394] __get_user_pages+0x204/0xb88 [ 6.486395] populate_vma_page_range+0xbc/0x1b8 [ 6.486396] __mm_populate+0xcc/0x1e0 [ 6.486397] __arm64_sys_mlockall+0x1d4/0x1f8 [ 6.486398] invoke_syscall+0x50/0x120 [ 6.486399] el0_svc_common.constprop.0+0x48/0xf0 [ 6.486400] do_el0_svc+0x24/0x38 [ 6.486400] el0_svc+0x34/0xf0 [ 6.486402] el0t_64_sync_handler+0xa0/0xe8 [ 6.486404] el0t_64_sync+0x198/0x1a0 Indeed finish_fault() takes a PTL spin lock without irq disablement. > > I am working on adding batched stats update functionality in the hope > that will fix the regression. Thanks! FYI, I have zeroed in the issue on to preempt_disable(). Dropping this from _pcpu_protect_return solves the regression. Unlike x86, arm64 does a preempt_disable when doing this_cpu_*. On a cursory look it seems like this is unnecessary - since we are doing preempt_enable() immediately after reading the pointer, CPU migration is possible anyways, so there is nothing to be gained by reading pcpu pointer with preemption disabled. I am investigating whether we can simply drop this in general.