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[209.85.220.65]) by mx.google.com with SMTPS id c24sor11587563pgg.30.2019.06.17.09.53.58 for (Google Transport Security); Mon, 17 Jun 2019 09:53:58 -0700 (PDT) Received-SPF: pass (google.com: domain of nadav.amit@gmail.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WK8FGkjU; spf=pass (google.com: domain of nadav.amit@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=nadav.amit@gmail.com; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=5GIOr0j5QD0GGMq5iNvz4pmaxjrJeMOWrcA3ngAjb7A=; b=WK8FGkjUVKq18qGzWscm8ahQHW1GUCF+ILUXe63ay3w9JUKolPUj+3YphhK0E8VUiO D3VHOeRgF69Os5dNYBD+3tBeL+QGWRxe4O1lUNffI+ciOxTZnQUOovBJ8QJgdVFafc4r vr9ia4ySytk0IJYT5noK89/yQrr24KTxwjB0P6wOHHrL6IXBMlSQnoyT65V9bcz8SQCW DT5wZDEmNGYbA9YuMMPBYvx3OLXoNdO+ZjLbq7Clkt9R8M322Au0gCU1XYbms5dQt9A3 L+pOus4Fm3NyuNx6wxOGaBpjSeM0X2q/+qEIzrCnDdowFRbhBFU73gJDmUhuaF/pQcMj BBUA== X-Google-Smtp-Source: APXvYqxQvlJR/5/Ch56UVr+neR0wtCeYjFoYvDMw4Dtm/ZsiOnsiu5rpaDFdeLO8KgOLgtgCCaiS3A== X-Received: by 2002:a63:5211:: with SMTP id g17mr46491750pgb.405.1560790437276; Mon, 17 Jun 2019 09:53:57 -0700 (PDT) Received: from [10.33.114.148] ([66.170.99.1]) by smtp.gmail.com with ESMTPSA id t14sm13687953pfl.62.2019.06.17.09.53.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 09:53:56 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 12.4 \(3445.104.11\)) Subject: Re: [RFC 00/10] Process-local memory allocations for hiding KVM secrets From: Nadav Amit In-Reply-To: Date: Mon, 17 Jun 2019 09:53:54 -0700 Cc: Dave Hansen , Alexander Graf , Thomas Gleixner , Marius Hillenbrand , kvm list , LKML , Kernel Hardening , Linux-MM , Alexander Graf , David Woodhouse , the arch/x86 maintainers , Peter Zijlstra Content-Transfer-Encoding: 7bit Message-Id: <5AA8BF10-8987-4FCB-870C-667A5228D97B@gmail.com> References: <20190612170834.14855-1-mhillenb@amazon.de> <58788f05-04c3-e71c-12c3-0123be55012c@amazon.com> <63b1b249-6bc7-ffd9-99db-d36dd3f1a962@intel.com> <698ca264-123d-46ae-c165-ed62ea149896@intel.com> To: Andy Lutomirski X-Mailer: Apple Mail (2.3445.104.11) X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: > On Jun 17, 2019, at 9:14 AM, Andy Lutomirski wrote: > > On Mon, Jun 17, 2019 at 9:09 AM Dave Hansen wrote: >> On 6/17/19 8:54 AM, Andy Lutomirski wrote: >>>>> Would that mean that with Meltdown affected CPUs we open speculation >>>>> attacks against the mmlocal memory from KVM user space? >>>> Not necessarily. There would likely be a _set_ of local PGDs. We could >>>> still have pair of PTI PGDs just like we do know, they'd just be a local >>>> PGD pair. >>> Unfortunately, this would mean that we need to sync twice as many >>> top-level entries when we context switch. >> >> Yeah, PTI sucks. :) >> >> For anyone following along at home, I'm going to go off into crazy >> per-cpu-pgds speculation mode now... Feel free to stop reading now. :) >> >> But, I was thinking we could get away with not doing this on _every_ >> context switch at least. For instance, couldn't 'struct tlb_context' >> have PGD pointer (or two with PTI) in addition to the TLB info? That >> way we only do the copying when we change the context. Or does that tie >> the implementation up too much with PCIDs? > > Hmm, that seems entirely reasonable. I think the nasty bit would be > figuring out all the interactions with PV TLB flushing. PV TLB > flushes already don't play so well with PCID tracking, and this will > make it worse. We probably need to rewrite all that code regardless. How is PCID (as you implemented) related to TLB flushing of kernel (not user) PTEs? These kernel PTEs would be global, so they would be invalidated from all the address-spaces using INVLPG, I presume. No? Having said that, the fact that every hypervisor implements PV-TLB completely differently might be unwarranted.