From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C570C77B73 for ; Thu, 25 May 2023 03:35:46 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id CF779900002; Wed, 24 May 2023 23:35:45 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id CA7736B0075; Wed, 24 May 2023 23:35:45 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id B9679900002; Wed, 24 May 2023 23:35:45 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id A9CC56B0074 for ; Wed, 24 May 2023 23:35:45 -0400 (EDT) Received: from smtpin20.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id 393D3120A8E for ; Thu, 25 May 2023 03:35:45 +0000 (UTC) X-FDA: 80827363050.20.8CB6B2A Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by imf29.hostedemail.com (Postfix) with ESMTP id 122BB120015 for ; Thu, 25 May 2023 03:35:41 +0000 (UTC) Authentication-Results: imf29.hostedemail.com; dkim=none; dmarc=pass (policy=none) header.from=arm.com; spf=pass (imf29.hostedemail.com: domain of anshuman.khandual@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=anshuman.khandual@arm.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1684985742; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PWZACgA4NY3AXJvQXsw8I/LKC6xtjfh/5/KIa8ixSVg=; b=i0rr9Oe9f0RK1OpAURpJc2QePEYp1XuxyN/9S9hHffMntAJvLAj1h/2fF1RbYFdeSpzKKp 9y7vcQM9V12YmXcaV3B7lPeC3VZWkKH0ApZHLuvnRwFjT3Uusi+FnrtyEQIqfOxp4/+0rT 9NrEskSpr7fmAIQ/brKccXQuk2j51Pw= ARC-Authentication-Results: i=1; imf29.hostedemail.com; dkim=none; dmarc=pass (policy=none) header.from=arm.com; spf=pass (imf29.hostedemail.com: domain of anshuman.khandual@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=anshuman.khandual@arm.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1684985742; a=rsa-sha256; cv=none; b=xfn/5QDFDd6ZhMRPgSW002Z9fycAkmTPf/WvRsdunx2zUIcYgwbi6FM5r7hm9rm8+Yf6Vl J3Yfgr0hgnuPlWUJLiGXdNUzAtXzOhdT07j0Z4EPpXCSAlvEu8ztm6LKMTzby7hw5Y/Xb5 Ur7HUxmLQfDAOTHaKk/PkLg7bbVfwwQ= Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EFBED1042; Wed, 24 May 2023 20:36:25 -0700 (PDT) Received: from [10.162.43.6] (unknown [10.162.43.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B0A8D3F762; Wed, 24 May 2023 20:35:38 -0700 (PDT) Message-ID: <592942c0-00dc-0317-0411-f9e17870fb11@arm.com> Date: Thu, 25 May 2023 09:05:35 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v4 09/36] arm64: Implement the new page table range API Content-Language: en-US To: "Matthew Wilcox (Oracle)" , linux-arch@vger.kernel.org Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Catalin Marinas , linux-arm-kernel@lists.infradead.org References: <20230315051444.3229621-1-willy@infradead.org> <20230315051444.3229621-10-willy@infradead.org> From: Anshuman Khandual In-Reply-To: <20230315051444.3229621-10-willy@infradead.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspamd-Queue-Id: 122BB120015 X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: bibbapg35tbtsgqa8cbutyg185xc8hw1 X-HE-Tag: 1684985741-854180 X-HE-Meta: U2FsdGVkX1/B8r28HlFtliXQUBJIq0S1t3mnWA5+G2+uTfCiv6sfYzjEmRsVgkhPy41rdxO8UvNoJKBV9gUTolMH8icAcQtW1tCAtwTYvb68YHhw5+nLpWsWzVw0f8tvDs7+fHRzYcSIsnSqAnMo3Aaq/RI5q7Z7/1iInsI9+QNfNJugbdmlnUB/FlBuIEm7o8b5ruHFuCrwmJ0gaUPUjVkQ7y07H0NxOGxASu+fM1lMfNyXMd+7wRhR/ISUyhYLRAc+6KJLI2gT9X+TFZHXgrGqv1sGn+Bwdt1amo5IOtaMg1WfDo2EKzfanWqMcYGozXp5fRLocfpCZ+tRrcBWN7jNC0TAOKF9dHQvzYtNlPrzpWUjU7UFJSE64lheC/h+yw0y9t83YokvLhcobupJjwMZrxcUopYXsa1L8TdsnzgjeWNUDN+Icl7rKHrjJa9XMVPTiK9SdXxWtbXTXaHeM9fhC8xUw7FdQRb93hXw7F0FILh2agNOTf7W0ZjdcgxCmeJjRG1GRnYmZSsvMv4mddY2ScMWCd43BGve1fShtpxbEv5WAtSA04MdPQfFu8AVnBjoo8BJEERxAk+k2TqHds+rxmdQxIakEsTf6c/DOBLrbauAytMJiEf1NtOnGDGYzvcj8ioOCqAivxu6MhjZsx4VTVIbp6ZMd0BM7WhidxHavvU+68BAFoQNRLuDVU19CUJ35D0Wc9RT8HOCRXAdow5mpF7J4C0H926C2ShGq/7XVlH2RTqwn3ttq5BDKxg0mH+7PxXkTnhCbOQ75S+1casCox7bgDWewv+zYQc2ktVekTGkZB4JQdzueFMNa2Jx6MuMDQ32Uf7HsabpBBJAMlyGqpSX35gWIMleNHnpmTZj7d1AOEQe7E4yWhnH6udMUZYghPEOzRq//CldQO3jPQyUbZ8zqdoDrdImYAO+Q90ayjAS2JQeQMJBM7byLdJ2f777kzSEDZxf5O0kYP7 dYffSsHE iYZUll6ULYHJ3G/Z4SXy2XKE3ck59fBYiDmOYZSMrlHYsIbE7c9RWipQeJv1KV0cjBvlS4HAOE3W3wJWx2Oe5aJfGM0MbtFjUR1fjEqdDtnudc1/BEGew+aysNagwnRqSf9pqlrLhmJyWXvJYH8lZRFXZ27+1cktsnrpLbCyCI2GXlMgj1UtuBHfAT+UxlQ60tbqa+sFBKMjOXQ/TiRZbO0Rbfttu99DKLaBL X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 3/15/23 10:44, Matthew Wilcox (Oracle) wrote: > Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). > Change the PG_dcache_clean flag from being per-page to per-folio. > > Signed-off-by: Matthew Wilcox (Oracle) > Reviewed-by: Catalin Marinas > Cc: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/include/asm/cacheflush.h | 4 +++- > arch/arm64/include/asm/pgtable.h | 25 ++++++++++++++------ > arch/arm64/mm/flush.c | 36 +++++++++++------------------ > 3 files changed, 35 insertions(+), 30 deletions(-) > > diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h > index 37185e978aeb..d115451ed263 100644 > --- a/arch/arm64/include/asm/cacheflush.h > +++ b/arch/arm64/include/asm/cacheflush.h > @@ -114,7 +114,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, > #define copy_to_user_page copy_to_user_page > > /* > - * flush_dcache_page is used when the kernel has written to the page > + * flush_dcache_folio is used when the kernel has written to the page > * cache page at virtual address page->virtual. > * > * If this page isn't mapped (ie, page_mapping == NULL), or it might > @@ -127,6 +127,8 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, > */ > #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 > extern void flush_dcache_page(struct page *); > +void flush_dcache_folio(struct folio *); This is giving a checkpatch.pl warning WARNING: function definition argument 'struct folio *' should also have an identifier name #36: FILE: arch/arm64/include/asm/cacheflush.h:130: +void flush_dcache_folio(struct folio *); total: 0 errors, 1 warnings, 111 lines checked > +#define flush_dcache_folio flush_dcache_folio > > static __always_inline void icache_inval_all_pou(void) > { > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index 9428748f4691..6fd012663a01 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -355,12 +355,21 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, > set_pte(ptep, pte); > } > > -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, > - pte_t *ptep, pte_t pte) > -{ > - page_table_check_ptes_set(mm, addr, ptep, pte, 1); > - return __set_pte_at(mm, addr, ptep, pte); > +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, > + pte_t *ptep, pte_t pte, unsigned int nr) > +{ > + page_table_check_ptes_set(mm, addr, ptep, pte, nr); > + > + for (;;) { > + __set_pte_at(mm, addr, ptep, pte); > + if (--nr == 0) > + break; > + ptep++; > + addr += PAGE_SIZE; > + pte_val(pte) += PAGE_SIZE; > + } > } > +#define set_ptes set_ptes > > /* > * Huge pte definitions. > @@ -1059,8 +1068,8 @@ static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) > /* > * On AArch64, the cache coherency is handled via the set_pte_at() function. > */ > -static inline void update_mmu_cache(struct vm_area_struct *vma, > - unsigned long addr, pte_t *ptep) > +static inline void update_mmu_cache_range(struct vm_area_struct *vma, > + unsigned long addr, pte_t *ptep, unsigned int nr) > { > /* > * We don't do anything here, so there's a very small chance of > @@ -1069,6 +1078,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, > */ > } > > +#define update_mmu_cache(vma, addr, ptep) \ > + update_mmu_cache_range(vma, addr, ptep, 1) > #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) > > #ifdef CONFIG_ARM64_PA_BITS_52 > diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c > index 5f9379b3c8c8..deb781af0a3a 100644 > --- a/arch/arm64/mm/flush.c > +++ b/arch/arm64/mm/flush.c > @@ -50,20 +50,13 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page, > > void __sync_icache_dcache(pte_t pte) > { > - struct page *page = pte_page(pte); > + struct folio *folio = page_folio(pte_page(pte)); > > - /* > - * HugeTLB pages are always fully mapped, so only setting head page's > - * PG_dcache_clean flag is enough. > - */ > - if (PageHuge(page)) > - page = compound_head(page); > - > - if (!test_bit(PG_dcache_clean, &page->flags)) { > - sync_icache_aliases((unsigned long)page_address(page), > - (unsigned long)page_address(page) + > - page_size(page)); > - set_bit(PG_dcache_clean, &page->flags); > + if (!test_bit(PG_dcache_clean, &folio->flags)) { > + sync_icache_aliases((unsigned long)folio_address(folio), > + (unsigned long)folio_address(folio) + > + folio_size(folio)); > + set_bit(PG_dcache_clean, &folio->flags); > } > } > EXPORT_SYMBOL_GPL(__sync_icache_dcache); > @@ -73,17 +66,16 @@ EXPORT_SYMBOL_GPL(__sync_icache_dcache); > * it as dirty for later flushing when mapped in user space (if executable, > * see __sync_icache_dcache). > */ > -void flush_dcache_page(struct page *page) > +void flush_dcache_folio(struct folio *folio) > { > - /* > - * HugeTLB pages are always fully mapped and only head page will be > - * set PG_dcache_clean (see comments in __sync_icache_dcache()). > - */ > - if (PageHuge(page)) > - page = compound_head(page); > + if (test_bit(PG_dcache_clean, &folio->flags)) > + clear_bit(PG_dcache_clean, &folio->flags); > +} > +EXPORT_SYMBOL(flush_dcache_folio); > > - if (test_bit(PG_dcache_clean, &page->flags)) > - clear_bit(PG_dcache_clean, &page->flags); > +void flush_dcache_page(struct page *page) > +{ > + flush_dcache_folio(page_folio(page)); > } > EXPORT_SYMBOL(flush_dcache_page); > Otherwise LGTM.