From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0753C4742C for ; Thu, 5 Nov 2020 11:13:16 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 5357520867 for ; Thu, 5 Nov 2020 11:13:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5357520867 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 76E466B00E2; Thu, 5 Nov 2020 06:13:15 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 71FF36B00E3; Thu, 5 Nov 2020 06:13:15 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 60B2C6B00E4; Thu, 5 Nov 2020 06:13:15 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0030.hostedemail.com [216.40.44.30]) by kanga.kvack.org (Postfix) with ESMTP id 2B01F6B00E2 for ; Thu, 5 Nov 2020 06:13:15 -0500 (EST) Received: from smtpin03.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id C1E86362A for ; Thu, 5 Nov 2020 11:13:14 +0000 (UTC) X-FDA: 77450103108.03.owner06_3911dbc272c9 Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin03.hostedemail.com (Postfix) with ESMTP id 24B4928A4EB for ; Thu, 5 Nov 2020 11:13:13 +0000 (UTC) X-HE-Tag: owner06_3911dbc272c9 X-Filterd-Recvd-Size: 6833 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by imf37.hostedemail.com (Postfix) with ESMTP for ; Thu, 5 Nov 2020 11:13:12 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6FDF142F; Thu, 5 Nov 2020 03:13:11 -0800 (PST) Received: from [10.37.12.41] (unknown [10.37.12.41]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 645273F66E; Thu, 5 Nov 2020 03:13:09 -0800 (PST) Subject: Re: [PATCH v8 30/43] arm64: kasan: Allow enabling in-kernel MTE To: Andrey Konovalov , Catalin Marinas Cc: Will Deacon , Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Branislav Rankov , Kevin Brodsky , Andrew Morton , kasan-dev@googlegroups.com, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org References: <5e3c76cac4b161fe39e3fc8ace614400bc2fb5b1.1604531793.git.andreyknvl@google.com> From: Vincenzo Frascino Message-ID: <58aae616-f1be-d626-de16-af48cc2512b0@arm.com> Date: Thu, 5 Nov 2020 11:16:10 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <5e3c76cac4b161fe39e3fc8ace614400bc2fb5b1.1604531793.git.andreyknvl@google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi Andrey, On 11/4/20 11:18 PM, Andrey Konovalov wrote: > Hardware tag-based KASAN relies on Memory Tagging Extension (MTE) > feature and requires it to be enabled. MTE supports > > This patch adds a new mte_init_tags() helper, that enables MTE in > Synchronous mode in EL1 and is intended to be called from KASAN runtime > during initialization. > > The Tag Checking operation causes a synchronous data abort as > a consequence of a tag check fault when MTE is configured in > synchronous mode. > > As part of this change enable match-all tag for EL1 to allow the > kernel to access user pages without faulting. This is required because > the kernel does not have knowledge of the tags set by the user in a > page. > > Note: For MTE, the TCF bit field in SCTLR_EL1 affects only EL1 in a > similar way as TCF0 affects EL0. > > MTE that is built on top of the Top Byte Ignore (TBI) feature hence we > enable it as part of this patch as well. > seems that in this patch you dropped me as author. Would you mind to clarify the reason? > Signed-off-by: Vincenzo Frascino > Co-developed-by: Andrey Konovalov > Signed-off-by: Andrey Konovalov > --- > Change-Id: I4d67497268bb7f0c2fc5dcacefa1e273df4af71d > --- > arch/arm64/include/asm/mte-kasan.h | 6 ++++++ > arch/arm64/kernel/mte.c | 7 +++++++ > arch/arm64/mm/proc.S | 23 ++++++++++++++++++++--- > 3 files changed, 33 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/include/asm/mte-kasan.h b/arch/arm64/include/asm/mte-kasan.h > index 3a70fb1807fd..ae75feaea2d4 100644 > --- a/arch/arm64/include/asm/mte-kasan.h > +++ b/arch/arm64/include/asm/mte-kasan.h > @@ -29,6 +29,8 @@ u8 mte_get_mem_tag(void *addr); > u8 mte_get_random_tag(void); > void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag); > > +void __init mte_init_tags(u64 max_tag); > + > #else /* CONFIG_ARM64_MTE */ > > static inline u8 mte_get_ptr_tag(void *ptr) > @@ -49,6 +51,10 @@ static inline void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) > return addr; > } > > +static inline void mte_init_tags(u64 max_tag) > +{ > +} > + > #endif /* CONFIG_ARM64_MTE */ > > #endif /* __ASSEMBLY__ */ > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index 06ba6c923ab7..fcfbefcc3174 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -121,6 +121,13 @@ void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) > return ptr; > } > > +void __init mte_init_tags(u64 max_tag) > +{ > + /* Enable MTE Sync Mode for EL1. */ > + sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_SYNC); > + isb(); I am fine with the approach of letting cpu_enable_mte() call directly kasan_init_tags(), but how does it work of the other 2 implementation of KASAN? Is it still called in arch_setup()? I would prefer to keep the code that initializes the sync mode in cpu_enable_mte() (calling kasan_init_tags() before then that) or in a separate function since setting the mode has nothing to do with initializing the tags. The second approach probably would come handy when we introduce async mode. > +} > + > static void update_sctlr_el1_tcf0(u64 tcf0) > { > /* ISB required for the kernel uaccess routines */ > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 23c326a06b2d..7c3304fb15d9 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -40,9 +40,15 @@ > #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA > > #ifdef CONFIG_KASAN_SW_TAGS > -#define TCR_KASAN_FLAGS TCR_TBI1 > +#define TCR_KASAN_SW_FLAGS TCR_TBI1 > #else > -#define TCR_KASAN_FLAGS 0 > +#define TCR_KASAN_SW_FLAGS 0 > +#endif > + > +#ifdef CONFIG_KASAN_HW_TAGS > +#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 > +#else > +#define TCR_KASAN_HW_FLAGS 0 > #endif > > /* > @@ -427,6 +433,10 @@ SYM_FUNC_START(__cpu_setup) > */ > mov_q x5, MAIR_EL1_SET > #ifdef CONFIG_ARM64_MTE > + mte_tcr .req x20 > + > + mov mte_tcr, #0 > + > /* > * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported > * (ID_AA64PFR1_EL1[11:8] > 1). > @@ -447,6 +457,9 @@ SYM_FUNC_START(__cpu_setup) > /* clear any pending tag check faults in TFSR*_EL1 */ > msr_s SYS_TFSR_EL1, xzr > msr_s SYS_TFSRE0_EL1, xzr > + > + /* set the TCR_EL1 bits */ > + mov_q mte_tcr, TCR_KASAN_HW_FLAGS > 1: > #endif > msr mair_el1, x5 > @@ -456,7 +469,11 @@ SYM_FUNC_START(__cpu_setup) > */ > mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ > TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ > - TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS > + TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS > +#ifdef CONFIG_ARM64_MTE > + orr x10, x10, mte_tcr > + .unreq mte_tcr > +#endif > tcr_clear_errata_bits x10, x9, x5 > > #ifdef CONFIG_ARM64_VA_BITS_52 > -- Regards, Vincenzo