x86: possible store-tearing in native_set_pte?

x86: possible store-tearing in native_set_pte?

[Nadav Amit]

Can someone please explain why it is ok for native_set_pte to assign the PTE
without WRITE_ONCE() ?

Couldn’t a PTE write be torn, and the PTE be prefetched in between (or even
used for translation by another core)?

I did not encounter this case, but it seems to me possible according to the
documentation:

Intel SDM 4.10.2.3 “Detail of TLB Use": "The processor may cache
translations required for prefetches and for accesses ... that would never
actually occur in the executed code path.”

Documentation/memory-barriers.txt: "The compiler is within its rights to
invent stores to a variable”.

Thanks,
Nadav
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Re: x86: possible store-tearing in native_set_pte?

[Nadav Amit]

Resending with fixed formatting (sorry for that):

Can someone please explain why it is ok for native_set_pte to assign
the PTE without WRITE_ONCE() ?

Isn't it possible for a PTE write to be torn, and the PTE to be
prefetched in between (or even used for translation by another core)?

I did not encounter this case, but it seems to me possible according
to the documentation:

Intel SDM 4.10.2.3 "Detail of TLB Use": "The processor may cache
translations required for prefetches and for accesses ... that would
never actually occur in the executed code path."

Documentation/memory-barriers.txt: "The compiler is within its rights
to invent stores to a variable".

Thanks,
Nadav

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Re: x86: possible store-tearing in native_set_pte?

[Vlastimil Babka]

On 04/26/2016 02:40 AM, Nadav Amit wrote:
> Resending with fixed formatting (sorry for that):
>
> Can someone please explain why it is ok for native_set_pte to assign
> the PTE without WRITE_ONCE() ?

You should probably ask also x86 maintainers/list. IMHO you might have a 
point, but I may be missing something.

> Isn't it possible for a PTE write to be torn, and the PTE to be
> prefetched in between (or even used for translation by another core)?
>
> I did not encounter this case, but it seems to me possible according
> to the documentation:
>
> Intel SDM 4.10.2.3 "Detail of TLB Use": "The processor may cache
> translations required for prefetches and for accesses ... that would
> never actually occur in the executed code path."
>
> Documentation/memory-barriers.txt: "The compiler is within its rights
> to invent stores to a variable".
>
> Thanks,
> Nadav
>
> --
> To unsubscribe, send a message with 'unsubscribe linux-mm' in
> the body to majordomo@kvack.org.  For more info on Linux MM,
> see: http://www.linux-mm.org/ .
> Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a>
>

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