From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ob0-f200.google.com (mail-ob0-f200.google.com [209.85.214.200]) by kanga.kvack.org (Postfix) with ESMTP id DC8396B0253 for ; Wed, 27 Apr 2016 11:05:51 -0400 (EDT) Received: by mail-ob0-f200.google.com with SMTP id n2so90858594obo.1 for ; Wed, 27 Apr 2016 08:05:51 -0700 (PDT) Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2on0066.outbound.protection.outlook.com. [207.46.100.66]) by mx.google.com with ESMTPS id 68si10335350iow.126.2016.04.27.08.05.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Apr 2016 08:05:50 -0700 (PDT) Subject: Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for AMD processors References: <20160426225553.13567.19459.stgit@tlendack-t1.amdoffice.net> <20160426225604.13567.55443.stgit@tlendack-t1.amdoffice.net> <5720D066.7080409@amd.com> From: Tom Lendacky Message-ID: <5720D546.6050105@amd.com> Date: Wed, 27 Apr 2016 10:05:42 -0500 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Andy Lutomirski Cc: linux-arch , "linux-efi@vger.kernel.org" , kvm list , "linux-doc@vger.kernel.org" , X86 ML , "linux-kernel@vger.kernel.org" , kasan-dev , "linux-mm@kvack.org" , iommu@lists.linux-foundation.org, =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Arnd Bergmann , Jonathan Corbet , Matt Fleming , Joerg Roedel , Konrad Rzeszutek Wilk , Paolo Bonzini , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Andrey Ryabinin , Alexander Potapenko , Thomas Gleixner , Dmitry Vyukov On 04/27/2016 09:47 AM, Andy Lutomirski wrote: > On Wed, Apr 27, 2016 at 7:44 AM, Tom Lendacky wrote: >> On 04/27/2016 09:33 AM, Andy Lutomirski wrote: >>> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky wrote: >>>> For AMD processors that support PAT, set the write-protect cache mode >>>> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). >>> >>> What's the purpose of using the WP memory type? >> >> The WP memory type is used for encrypting or decrypting data "in place". >> The use of the WP on the source data will prevent any of the source >> data from being cached. Refer to section 7.10.8 "Encrypt-in-Place" in >> the AMD64 APM link provided in the cover letter. >> >> This memory type will be used in subsequent patches for this purpose. > > OK. > > Why AMD-only? I thought Intel supported WP, too. Just me being conservative. If there aren't any objections from the Intel folks about it we can remove the vendor check and just set it. Thanks, Tom > > --Andy > -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org