From: Nadav Amit <nadav.amit@gmail.com>
To: Rik van Riel <riel@surriel.com>
Cc: the arch/x86 maintainers <x86@kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Borislav Petkov <bp@alien8.de>,
peterz@infradead.org, Dave Hansen <dave.hansen@linux.intel.com>,
zhengqi.arch@bytedance.com, thomas.lendacky@amd.com,
kernel-team@meta.com,
"open list:MEMORY MANAGEMENT" <linux-mm@kvack.org>,
Andrew Morton <akpm@linux-foundation.org>,
jannh@google.com, mhklinux@outlook.com,
andrew.cooper3@citrix.com
Subject: Re: [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code
Date: Mon, 20 Jan 2025 20:56:57 +0200 [thread overview]
Message-ID: <5501C6EC-38C7-472F-B129-F7A5144C3096@gmail.com> (raw)
In-Reply-To: <11fcbbbb545576a1bfa54839cf87a72faf5603ab.camel@surriel.com>
> On 20 Jan 2025, at 19:56, Rik van Riel <riel@surriel.com> wrote:
>
> How would you keep track of CPUs where the tlbsync
> has NOT happened before arch_tlbbatch_flush()?
>
> That part seems to be missing still.
You only keep track if there is a pending tlbsync on *your* CPU. No need to
track if other CPUs did not issue tlbsync during arch_tlbbatch_add_pending().
If the process that does the reclamation was migrated, a TLBSYNC is issued
during the context switch, before that thread that does the reclamation has
any chance of being scheduled.
I hope this code changes on top of your would make it clearer:
> +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch,
> + struct mm_struct *mm,
> + unsigned long uaddr)
> +{
> + if (static_cpu_has(X86_FEATURE_INVLPGB) && mm_global_asid(mm)) {
> + u16 asid = mm_global_asid(mm);
> + /*
> + * Queue up an asynchronous invalidation. The corresponding
> + * TLBSYNC is done in arch_tlbbatch_flush(), and must be done
> + * on the same CPU.
> + */
#if 0 // remove
> + if (!batch->used_invlpgb) {
> + batch->used_invlpgb = true;
> + migrate_disable();
> + }
#endif
batch->used_invlpg = true;
preempt_disable();
> + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false);
> + /* Do any CPUs supporting INVLPGB need PTI? */
> + if (static_cpu_has(X86_FEATURE_PTI))
> + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false);
this_cpu_write(cpu_tlbstate.pending_tlbsync, true);
preempt_enable();
> +
> + /*
> + * Some CPUs might still be using a local ASID for this
> + * process, and require IPIs, while others are using the
> + * global ASID.
> + *
> + * In this corner case we need to do both the broadcast
> + * TLB invalidation, and send IPIs. The IPIs will help
> + * stragglers transition to the broadcast ASID.
> + */
> + if (READ_ONCE(mm->context.asid_transition))
> + goto also_send_ipi;
> + } else {
> +also_send_ipi:
> + inc_mm_tlb_gen(mm);
> + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
> + }
> + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
> +}
> +
Then in switch_mm_irqs_off(), b
if (this_cpu_read(cpu_tlbstate.pending_tlbsync))
tlbsync();
Note that when switch_mm_irqs_off() is called due to context switch from
context_switch(), finish_task_switch() has still not took place, so the
task cannot be scheduled on other cores.
next prev parent reply other threads:[~2025-01-20 18:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-16 2:30 [PATCH v5 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-01-16 2:30 ` [PATCH v5 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-16 2:30 ` [PATCH v5 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-16 2:30 ` [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-17 19:23 ` Michael Kelley
2025-01-17 19:32 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-16 2:30 ` [PATCH v5 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-16 2:30 ` [PATCH v5 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-16 2:30 ` [PATCH v5 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-16 2:30 ` [PATCH v5 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20 9:56 ` Nadav Amit
2025-01-20 14:02 ` Rik van Riel
2025-01-20 14:14 ` Nadav Amit
2025-01-20 16:11 ` Rik van Riel
2025-01-20 17:09 ` Nadav Amit
2025-01-20 17:11 ` Rik van Riel
2025-01-20 17:50 ` Nadav Amit
2025-01-20 17:56 ` Rik van Riel
2025-01-20 18:56 ` Nadav Amit [this message]
2025-01-21 2:33 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-16 2:30 ` [PATCH v5 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-16 18:14 ` [PATCH v5 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-16 22:37 ` Peter Zijlstra
2025-01-17 0:00 ` Andrew Cooper
2025-01-21 10:45 ` Peter Zijlstra
2025-01-21 17:14 ` Dave Hansen
2025-01-21 21:24 ` Michael Kelley
2025-01-21 17:22 ` Jann Horn
2025-01-21 21:39 ` Michael Kelley
2025-01-21 21:56 ` Jann Horn
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