From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFE6BE7716E for ; Thu, 5 Dec 2024 17:40:56 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 6F9286B00DD; Thu, 5 Dec 2024 12:40:56 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 681E26B014B; Thu, 5 Dec 2024 12:40:56 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 522D66B00E2; Thu, 5 Dec 2024 12:40:56 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0016.hostedemail.com [216.40.44.16]) by kanga.kvack.org (Postfix) with ESMTP id 2F2BE6B014B for ; Thu, 5 Dec 2024 12:40:56 -0500 (EST) Received: from smtpin12.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id DA9D81413EB for ; Thu, 5 Dec 2024 17:40:55 +0000 (UTC) X-FDA: 82861620450.12.BCDBC12 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by imf26.hostedemail.com (Postfix) with ESMTP id 37511140020 for ; Thu, 5 Dec 2024 17:40:40 +0000 (UTC) Authentication-Results: imf26.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf26.hostedemail.com: domain of alex@ghiti.fr designates 217.70.183.201 as permitted sender) smtp.mailfrom=alex@ghiti.fr ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1733420439; a=rsa-sha256; cv=none; b=jKU++qxYpwSP/sfXFG1gnCFoCTC0jRaVPSe4vhu6stfUn5k9mh5ebZYfZoG33fFb840ZpL vItFCqM9cIo3f9VpZfLThEahWPD/4cHgOjNsZsGVQcb+63vGCjE11bcDGQwWA4vWfWLtMT 7e8OFcTjrFWYrahO3CCjmpO7TWxj9II= ARC-Authentication-Results: i=1; imf26.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf26.hostedemail.com: domain of alex@ghiti.fr designates 217.70.183.201 as permitted sender) smtp.mailfrom=alex@ghiti.fr ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1733420439; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LNhajIgP33snUFkRioBbdmu/o02YpvYIzNslf1h2Sus=; b=5H1gLx5ZrhkqNTkPDK3xL0ts882aFuDuFEXnyUt0kBLrigwUbRVDO8uYYGq3FUCayejWBK 9LfHvnFTA7ueqnbJo6WfsetREqETBIEkDnwoEKq9OTNQzR7oBl58EkcpZ/DONw6yCLAjOQ l1koOZjSLgSXQF4F732WbeZUk6LgIWc= Received: by mail.gandi.net (Postfix) with ESMTPSA id 236B51BF203; Thu, 5 Dec 2024 17:40:45 +0000 (UTC) Message-ID: <528505d0-e0ba-414b-ad9d-bc78c07464a1@ghiti.fr> Date: Thu, 5 Dec 2024 18:40:44 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] riscv/ptrace: add new regset to access original a0 register Content-Language: en-US To: Celeste Liu , Oleg Nesterov , Paul Walmsley , Palmer Dabbelt , Albert Ou , Eric Biederman , Kees Cook , Shuah Khan Cc: "Dmitry V. Levin" , Andrea Bolognani , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Thomas Gleixner , Ron Economos , Charlie Jenkins , Quan Zhou , Felix Yan , Ruizhe Pan , Shiqi Zhang , Guo Ren , Yao Zi , Han Gao , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, stable@vger.kernel.org, linux-kselftest@vger.kernel.org References: <20241203-riscv-new-regset-v2-0-d37da8c0cba6@coelacanthus.name> <20241203-riscv-new-regset-v2-1-d37da8c0cba6@coelacanthus.name> From: Alexandre Ghiti In-Reply-To: <20241203-riscv-new-regset-v2-1-d37da8c0cba6@coelacanthus.name> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-GND-Sasl: alex@ghiti.fr X-Stat-Signature: wbk55mh7mr49rg1w6asa1wh3m373u5kg X-Rspam-User: X-Rspamd-Queue-Id: 37511140020 X-Rspamd-Server: rspam08 X-HE-Tag: 1733420440-350899 X-HE-Meta: U2FsdGVkX1+IPJBISzspvMoruw2kXebHmAFrapQE/DuvZtdf+Yj1cs+lTc/0qJL6zZkt4GlkpYtQDAq2f7ENCLuS3soygCrotTAeSZkMfporkgHQBr9agQU2HyefozxM5iLHZYhPFe2cCsPWekjCNkSzQwKieAPiYiQmd0tSoVmu5ieqlbHcT/VwRyf/dMESPMQgHDHBz6j88KwfRlPBklYM4dEF1lelRDOqJhegsODKAnJa5EFXS4KIfC4TeElS9M/45J4ap7mD3HZ9yX8e9hrnARya/vTf6nAH6ecs2aNvpVHGkRv/DtzRzRV57BN/WqLCyNjxncduHMQLc8IeVykGpCoA0xHoO6NRIngnREwrGxKHyX+VIPfdCAgzW3oTwXpfpGdfJedwbahbMV3RS6da0VUbhMSyNMSiSiPPwaYl5cLqK3gDmui6A4zqOh0CcZmBTDY6D5nh5FUrWX9rJ+cbZI7iH2fMbbBHUZq4hPPYFalPvovjtdwgFGNZocDTYFhDLcQSYIg2w6fTq4owHlrIvaD05m5iY0rTU/MrjPb/i5n2E1AvgEXVZOrN2c2LC9Dok9nde0Qt+Qmd49KlrTHS5V3/CHwGNJ+3IceiRGFU3ueJ+qF67KAKpO4CBsvm6j1rk3Jy3YLuQgDBCpokF+ufc2O3LCsOehayLAkPvZ7FDYA5yaOt5rQxyTD1t3GmNtp9n0Cfpcyhdwjy/Ei1OphS/FOgieV8H+7gKOG2xi1y/vKvvnJtG9ErnLw8mGAUJipVdmJfcheN2VWoVeLrgniOZoJ0X4md4M5mpqJ2OhDq6MAtMC8WDnvu5PE5i8o1JbkrNnUQ4OdRpxEhyx/Ukgzkdz1nCcMbY1O/Yi+5Ka6yeNgiLCumh3nvPXyu5aoiKYyCCzd3l6+b5PSsOWTtdIKeWW1+hTqPSJuckR6WmRKgALKE1/2XJ8Tr1uko5ElcxZeI3eGRWnuPNaDkWk8 Oh8b28Kg u8xXMKc14YcT13s711/hqxDFM3WKA/F1XXwdVsrG4yWUJi99H9Lx18jDy+7Yp2mtUF9aJVd3OiCCCkBhtX0e/udcE9G+AuSkDzSJsimKdOtDUN/Puab5Ouwv18XpGCLHFA1zalzl0PggQwvGIiJyUNBjpJxOIkKEVgObb X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Celeste, On 03/12/2024 10:30, Celeste Liu wrote: > The orig_a0 is missing in struct user_regs_struct of riscv, and there is > no way to add it without breaking UAPI. (See Link tag below) > > Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to > access original a0 register from userspace via ptrace API. > > Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmail.com/ > Cc: stable@vger.kernel.org > Signed-off-by: Celeste Liu > --- > arch/riscv/kernel/ptrace.c | 32 ++++++++++++++++++++++++++++++++ > include/uapi/linux/elf.h | 1 + > 2 files changed, 33 insertions(+) > > diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c > index ea67e9fb7a583683b922fe2c017ea61f3bc848db..18ce07ffb27bb1180667769eed800f6fdf96c083 100644 > --- a/arch/riscv/kernel/ptrace.c > +++ b/arch/riscv/kernel/ptrace.c > @@ -31,6 +31,7 @@ enum riscv_regset { > #ifdef CONFIG_RISCV_ISA_SUPM > REGSET_TAGGED_ADDR_CTRL, > #endif > + REGSET_ORIG_A0, > }; > > static int riscv_gpr_get(struct task_struct *target, > @@ -184,6 +185,29 @@ static int tagged_addr_ctrl_set(struct task_struct *target, > } > #endif > > +static int riscv_orig_a0_get(struct task_struct *target, > + const struct user_regset *regset, > + struct membuf to) > +{ > + return membuf_store(&to, task_pt_regs(target)->orig_a0); > +} > + > +static int riscv_orig_a0_set(struct task_struct *target, > + const struct user_regset *regset, > + unsigned int pos, unsigned int count, > + const void *kbuf, const void __user *ubuf) > +{ > + unsigned long orig_a0 = task_pt_regs(target)->orig_a0; > + int ret; > + > + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &orig_a0, 0, -1); > + if (ret) > + return ret; > + > + task_pt_regs(target)->orig_a0 = orig_a0; > + return ret; > +} > + > static const struct user_regset riscv_user_regset[] = { > [REGSET_X] = { > .core_note_type = NT_PRSTATUS, > @@ -224,6 +248,14 @@ static const struct user_regset riscv_user_regset[] = { > .set = tagged_addr_ctrl_set, > }, > #endif > + [REGSET_ORIG_A0] = { > + .core_note_type = NT_RISCV_ORIG_A0, > + .n = 1, > + .size = sizeof(elf_greg_t), > + .align = sizeof(elf_greg_t), > + .regset_get = riscv_orig_a0_get, > + .set = riscv_orig_a0_set, > + }, > }; > > static const struct user_regset_view riscv_user_native_view = { > diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h > index b44069d29cecc0f9de90ee66bfffd2137f4275a8..390060229601631da2fb27030d9fa2142e676c14 100644 > --- a/include/uapi/linux/elf.h > +++ b/include/uapi/linux/elf.h > @@ -452,6 +452,7 @@ typedef struct elf64_shdr { > #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ > #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ > #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */ > +#define NT_RISCV_ORIG_A0 0x903 /* RISC-V original a0 register */ > #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ > #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ > #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ > Do you know how far this should be backported? Does the following fixes tag make sense? Fixes: e2c0cdfba7f6 ("RISC-V: User-facing API") Thanks, Alex