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From: Alexandre Ghiti <alex@ghiti.fr>
To: Celeste Liu <uwu@coelacanthus.name>,
	Oleg Nesterov <oleg@redhat.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Eric Biederman <ebiederm@xmission.com>,
	Kees Cook <kees@kernel.org>, Shuah Khan <shuah@kernel.org>
Cc: "Dmitry V. Levin" <ldv@strace.io>,
	"Andrea Bolognani" <abologna@redhat.com>,
	"Björn Töpel" <bjorn@kernel.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Ron Economos" <re@w6rz.net>,
	"Charlie Jenkins" <charlie@rivosinc.com>,
	"Quan Zhou" <zhouquan@iscas.ac.cn>,
	"Felix Yan" <felixonmars@archlinux.org>,
	"Ruizhe Pan" <c141028@gmail.com>,
	"Shiqi Zhang" <shiqi@isrc.iscas.ac.cn>,
	"Guo Ren" <guoren@kernel.org>, "Yao Zi" <ziyao@disroot.org>,
	"Han Gao" <gaohan@iscas.ac.cn>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, stable@vger.kernel.org,
	linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 1/2] riscv/ptrace: add new regset to access original a0 register
Date: Thu, 5 Dec 2024 18:40:44 +0100	[thread overview]
Message-ID: <528505d0-e0ba-414b-ad9d-bc78c07464a1@ghiti.fr> (raw)
In-Reply-To: <20241203-riscv-new-regset-v2-1-d37da8c0cba6@coelacanthus.name>

Hi Celeste,

On 03/12/2024 10:30, Celeste Liu wrote:
> The orig_a0 is missing in struct user_regs_struct of riscv, and there is
> no way to add it without breaking UAPI. (See Link tag below)
>
> Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to
> access original a0 register from userspace via ptrace API.
>
> Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmail.com/
> Cc: stable@vger.kernel.org
> Signed-off-by: Celeste Liu <uwu@coelacanthus.name>
> ---
>   arch/riscv/kernel/ptrace.c | 32 ++++++++++++++++++++++++++++++++
>   include/uapi/linux/elf.h   |  1 +
>   2 files changed, 33 insertions(+)
>
> diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
> index ea67e9fb7a583683b922fe2c017ea61f3bc848db..18ce07ffb27bb1180667769eed800f6fdf96c083 100644
> --- a/arch/riscv/kernel/ptrace.c
> +++ b/arch/riscv/kernel/ptrace.c
> @@ -31,6 +31,7 @@ enum riscv_regset {
>   #ifdef CONFIG_RISCV_ISA_SUPM
>   	REGSET_TAGGED_ADDR_CTRL,
>   #endif
> +	REGSET_ORIG_A0,
>   };
>   
>   static int riscv_gpr_get(struct task_struct *target,
> @@ -184,6 +185,29 @@ static int tagged_addr_ctrl_set(struct task_struct *target,
>   }
>   #endif
>   
> +static int riscv_orig_a0_get(struct task_struct *target,
> +			     const struct user_regset *regset,
> +			     struct membuf to)
> +{
> +	return membuf_store(&to, task_pt_regs(target)->orig_a0);
> +}
> +
> +static int riscv_orig_a0_set(struct task_struct *target,
> +			     const struct user_regset *regset,
> +			     unsigned int pos, unsigned int count,
> +			     const void *kbuf, const void __user *ubuf)
> +{
> +	unsigned long orig_a0 = task_pt_regs(target)->orig_a0;
> +	int ret;
> +
> +	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &orig_a0, 0, -1);
> +	if (ret)
> +		return ret;
> +
> +	task_pt_regs(target)->orig_a0 = orig_a0;
> +	return ret;
> +}
> +
>   static const struct user_regset riscv_user_regset[] = {
>   	[REGSET_X] = {
>   		.core_note_type = NT_PRSTATUS,
> @@ -224,6 +248,14 @@ static const struct user_regset riscv_user_regset[] = {
>   		.set = tagged_addr_ctrl_set,
>   	},
>   #endif
> +	[REGSET_ORIG_A0] = {
> +		.core_note_type = NT_RISCV_ORIG_A0,
> +		.n = 1,
> +		.size = sizeof(elf_greg_t),
> +		.align = sizeof(elf_greg_t),
> +		.regset_get = riscv_orig_a0_get,
> +		.set = riscv_orig_a0_set,
> +	},
>   };
>   
>   static const struct user_regset_view riscv_user_native_view = {
> diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
> index b44069d29cecc0f9de90ee66bfffd2137f4275a8..390060229601631da2fb27030d9fa2142e676c14 100644
> --- a/include/uapi/linux/elf.h
> +++ b/include/uapi/linux/elf.h
> @@ -452,6 +452,7 @@ typedef struct elf64_shdr {
>   #define NT_RISCV_CSR	0x900		/* RISC-V Control and Status Registers */
>   #define NT_RISCV_VECTOR	0x901		/* RISC-V vector registers */
>   #define NT_RISCV_TAGGED_ADDR_CTRL 0x902	/* RISC-V tagged address control (prctl()) */
> +#define NT_RISCV_ORIG_A0	  0x903	/* RISC-V original a0 register */
>   #define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers */
>   #define NT_LOONGARCH_CSR	0xa01	/* LoongArch control and status registers */
>   #define NT_LOONGARCH_LSX	0xa02	/* LoongArch Loongson SIMD Extension registers */
>

Do you know how far this should be backported? Does the following fixes 
tag make sense?

Fixes: e2c0cdfba7f6 ("RISC-V: User-facing API")

Thanks,

Alex



  parent reply	other threads:[~2024-12-05 17:40 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-03  9:30 [PATCH v2 0/2] " Celeste Liu
2024-12-03  9:30 ` [PATCH v2 1/2] " Celeste Liu
2024-12-03 11:35   ` Björn Töpel
2024-12-05 17:40   ` Alexandre Ghiti [this message]
2024-12-03  9:30 ` [PATCH v2 2/2] riscv: selftests: Add a ptrace test to verify syscall parameter modification Celeste Liu
2024-12-03 11:38   ` Björn Töpel
2024-12-03 12:55   ` Andrew Jones
2024-12-19 18:26     ` Charlie Jenkins
2024-12-19 21:29       ` Celeste Liu
2024-12-19 21:36         ` Charlie Jenkins
2024-12-26 11:04           ` Celeste Liu

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