From: "Verma, Vishal L" <vishal.l.verma@intel.com>
To: "Williams, Dan J" <dan.j.williams@intel.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>
Cc: "linux-mm@kvack.org" <linux-mm@kvack.org>,
"fan.ni@samsung.com" <fan.ni@samsung.com>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>
Subject: Re: [PATCH v2 13/20] cxl/region: Add region autodiscovery
Date: Sat, 11 Feb 2023 00:29:02 +0000 [thread overview]
Message-ID: <4f10837c5dcc405eac2441aa78a5f2f388fb601a.camel@intel.com> (raw)
In-Reply-To: <167601999958.1924368.9366954455835735048.stgit@dwillia2-xfh.jf.intel.com>
On Fri, 2023-02-10 at 01:06 -0800, Dan Williams wrote:
> Region autodiscovery is an asynchronous state machine advanced by
> cxl_port_probe(). After the decoders on an endpoint port are enumerated
> they are scanned for actively enabled instances. Each active decoder is
> flagged for auto-assembly CXL_DECODER_F_AUTO and attached to a region.
> If a region does not already exist for the address range setting of the
> decoder one is created. That creation process may race with other
> decoders of the same region being discovered since cxl_port_probe() is
> asynchronous. A new 'struct cxl_root_decoder' lock, @range_lock, is
> introduced to mitigate that race.
>
> Once all decoders have arrived, "p->nr_targets == p->interleave_ways",
> they are sorted by their relative decode position. The sort algorithm
> involves finding the point in the cxl_port topology where one leg of the
> decode leads to deviceA and the other deviceB. At that point in the
> topology the target order in the 'struct cxl_switch_decoder' indicates
> the relative position of those endpoint decoders in the region.
>
> > From that point the region goes through the same setup and validation
> steps as user-created regions, but instead of programming the decoders
> it validates that driver would have written the same values to the
> decoders as were already present.
>
> Tested-by: Fan Ni <fan.ni@samsung.com>
> Link: https://lore.kernel.org/r/167564540972.847146.17096178433176097831.stgit@dwillia2-xfh.jf.intel.com
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> drivers/cxl/core/hdm.c | 11 +
> drivers/cxl/core/port.c | 2
> drivers/cxl/core/region.c | 497 ++++++++++++++++++++++++++++++++++++++++++++-
> drivers/cxl/cxl.h | 29 +++
> drivers/cxl/port.c | 48 ++++
> 5 files changed, 576 insertions(+), 11 deletions(-)
>
>
One question below, but otherwise looks good,
Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>
<..>
>
> +static int cxl_region_attach_auto(struct cxl_region *cxlr,
> + struct cxl_endpoint_decoder *cxled, int pos)
> +{
> + struct cxl_region_params *p = &cxlr->params;
> +
> + if (cxled->state != CXL_DECODER_STATE_AUTO) {
> + dev_err(&cxlr->dev,
> + "%s: unable to add decoder to autodetected region\n",
> + dev_name(&cxled->cxld.dev));
> + return -EINVAL;
> + }
> +
> + if (pos >= 0) {
> + dev_dbg(&cxlr->dev, "%s: expected auto position, not %d\n",
> + dev_name(&cxled->cxld.dev), pos);
> + return -EINVAL;
> + }
> +
> + if (p->nr_targets >= p->interleave_ways) {
> + dev_err(&cxlr->dev, "%s: no more target slots available\n",
> + dev_name(&cxled->cxld.dev));
> + return -ENXIO;
> + }
> +
> + /*
> + * Temporarily record the endpoint decoder into the target array. Yes,
> + * this means that userspace can view devices in the wrong position
> + * before the region activates, and must be careful to understand when
> + * it might be racing region autodiscovery.
> + */
Would it be worthwhile adding an attribute around this - either to
distinguish an auto-assembled region from a user-created one, or
perhaps better - something to mark the assembly complete? cxl-list
doesn't have to display this attribute as is, but maybe it can make a
decision to mark it as idle while assembly is pending, or maybe even
refuse to add_cxl_region() for it entirely?
This can be a follow-on too.
> + pos = p->nr_targets;
> + p->targets[pos] = cxled;
> + cxled->pos = pos;
> + p->nr_targets++;
> +
> + return 0;
> +}
> +
>
next prev parent reply other threads:[~2023-02-11 0:29 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 9:05 [PATCH v2 00/20] CXL RAM and the 'Soft Reserved' => 'System RAM' default Dan Williams
2023-02-10 9:05 ` [PATCH v2 01/20] cxl/memdev: Fix endpoint port removal Dan Williams
2023-02-10 17:28 ` Jonathan Cameron
2023-02-10 21:14 ` Dan Williams
2023-02-10 23:17 ` Verma, Vishal L
2023-02-10 9:05 ` [PATCH v2 02/20] cxl/Documentation: Update references to attributes added in v6.0 Dan Williams
2023-02-10 9:05 ` [PATCH v2 03/20] cxl/region: Add a mode attribute for regions Dan Williams
2023-02-10 9:05 ` [PATCH v2 04/20] cxl/region: Support empty uuids for non-pmem regions Dan Williams
2023-02-10 17:30 ` Jonathan Cameron
2023-02-10 23:34 ` Ira Weiny
2023-02-10 9:05 ` [PATCH v2 05/20] cxl/region: Validate region mode vs decoder mode Dan Williams
2023-02-10 9:05 ` [PATCH v2 06/20] cxl/region: Add volatile region creation support Dan Williams
2023-02-10 9:06 ` [PATCH v2 07/20] cxl/region: Refactor attach_target() for autodiscovery Dan Williams
2023-02-10 9:06 ` [PATCH v2 08/20] cxl/region: Cleanup target list on attach error Dan Williams
2023-02-10 17:31 ` Jonathan Cameron
2023-02-10 23:17 ` Verma, Vishal L
2023-02-10 23:46 ` Ira Weiny
2023-02-10 9:06 ` [PATCH v2 09/20] cxl/region: Move region-position validation to a helper Dan Williams
2023-02-10 17:34 ` Jonathan Cameron
2023-02-10 9:06 ` [PATCH v2 10/20] kernel/range: Uplevel the cxl subsystem's range_contains() helper Dan Williams
2023-02-10 9:06 ` [PATCH v2 11/20] cxl/region: Enable CONFIG_CXL_REGION to be toggled Dan Williams
2023-02-10 9:06 ` [PATCH v2 12/20] cxl/port: Split endpoint and switch port probe Dan Williams
2023-02-10 17:41 ` Jonathan Cameron
2023-02-10 23:21 ` Verma, Vishal L
2023-02-10 9:06 ` [PATCH v2 13/20] cxl/region: Add region autodiscovery Dan Williams
2023-02-10 18:09 ` Jonathan Cameron
2023-02-10 21:35 ` Dan Williams
2023-02-14 13:23 ` Jonathan Cameron
2023-02-14 16:43 ` Dan Williams
2023-02-10 21:49 ` Dan Williams
2023-02-11 0:29 ` Verma, Vishal L [this message]
2023-02-11 1:03 ` Dan Williams
[not found] ` <CGME20230213192752uscas1p1c49508da4b100c9ba6a1a3aa92ca03e5@uscas1p1.samsung.com>
2023-02-13 19:27 ` Fan Ni
[not found] ` <CGME20230228185348uscas1p1a5314a077383ee81ac228c1b9f1da2f8@uscas1p1.samsung.com>
2023-02-28 18:53 ` Fan Ni
2023-02-10 9:06 ` [PATCH v2 14/20] tools/testing/cxl: Define a fixed volatile configuration to parse Dan Williams
2023-02-10 18:12 ` Jonathan Cameron
2023-02-10 18:36 ` Dave Jiang
2023-02-11 0:39 ` Verma, Vishal L
2023-02-10 9:06 ` [PATCH v2 15/20] dax/hmem: Move HMAT and Soft reservation probe initcall level Dan Williams
2023-02-10 21:53 ` Dave Jiang
2023-02-10 21:57 ` Dave Jiang
2023-02-11 0:40 ` Verma, Vishal L
2023-02-10 9:06 ` [PATCH v2 16/20] dax/hmem: Drop unnecessary dax_hmem_remove() Dan Williams
2023-02-10 21:59 ` Dave Jiang
2023-02-11 0:41 ` Verma, Vishal L
2023-02-10 9:07 ` [PATCH v2 17/20] dax/hmem: Convey the dax range via memregion_info() Dan Williams
2023-02-10 22:03 ` Dave Jiang
2023-02-11 4:25 ` Verma, Vishal L
2023-02-10 9:07 ` [PATCH v2 18/20] dax/hmem: Move hmem device registration to dax_hmem.ko Dan Williams
2023-02-10 18:25 ` Jonathan Cameron
2023-02-10 22:09 ` Dave Jiang
2023-02-11 4:41 ` Verma, Vishal L
2023-02-10 9:07 ` [PATCH v2 19/20] dax: Assign RAM regions to memory-hotplug by default Dan Williams
2023-02-10 22:19 ` Dave Jiang
2023-02-11 5:57 ` Verma, Vishal L
2023-02-10 9:07 ` [PATCH v2 20/20] cxl/dax: Create dax devices for CXL RAM regions Dan Williams
2023-02-10 18:38 ` Jonathan Cameron
2023-02-10 22:42 ` Dave Jiang
2023-02-10 17:53 ` [PATCH v2 00/20] CXL RAM and the 'Soft Reserved' => 'System RAM' default Dan Williams
2023-02-11 14:04 ` Gregory Price
2023-02-13 18:22 ` Gregory Price
2023-02-13 18:31 ` Gregory Price
[not found] ` <CGME20230222214151uscas1p26d53b2e198f63a1f382fe575c6c25070@uscas1p2.samsung.com>
2023-02-22 21:41 ` Fan Ni
2023-02-22 22:18 ` Dan Williams
2023-02-14 13:35 ` Jonathan Cameron
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4f10837c5dcc405eac2441aa78a5f2f388fb601a.camel@intel.com \
--to=vishal.l.verma@intel.com \
--cc=dan.j.williams@intel.com \
--cc=dave.hansen@linux.intel.com \
--cc=fan.ni@samsung.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-mm@kvack.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox