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Fri, 9 Apr 2021 11:15:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at c-s.fr Received: from pegase1.c-s.fr ([192.168.12.234]) by localhost (pegase1.c-s.fr [192.168.12.234]) (amavisd-new, port 10024) with ESMTP id aoj9GNiSLPS0; Fri, 9 Apr 2021 11:15:57 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase1.c-s.fr (Postfix) with ESMTP id 4FGstj5712z9vBLh; Fri, 9 Apr 2021 11:15:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id BE2688B7E0; Fri, 9 Apr 2021 11:15:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id MgQO5aHk9mtP; Fri, 9 Apr 2021 11:15:58 +0200 (CEST) Received: from [192.168.4.90] (unknown [192.168.4.90]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 30DC68B7DE; Fri, 9 Apr 2021 11:15:58 +0200 (CEST) Subject: Re: [PATCH v3 4/9] powerpc/mm/book3s64: Fix possible build error To: "Aneesh Kumar K.V" , linux-mm@kvack.org, akpm@linux-foundation.org Cc: kaleshsingh@google.com, npiggin@gmail.com, joel@joelfernandes.org, linuxppc-dev@lists.ozlabs.org References: <20210330060752.592769-1-aneesh.kumar@linux.ibm.com> <20210330060752.592769-5-aneesh.kumar@linux.ibm.com> From: Christophe Leroy Message-ID: <4967af87-26be-ee91-b313-8c4729c42458@csgroup.eu> Date: Fri, 9 Apr 2021 11:15:56 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.0 MIME-Version: 1.0 In-Reply-To: <20210330060752.592769-5-aneesh.kumar@linux.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 3FF3EC0007D9 X-Stat-Signature: uy1tbgzmroxtkrk5686efqb6k446w65q Received-SPF: none (csgroup.eu>: No applicable sender policy available) receiver=imf03; identity=mailfrom; envelope-from=""; helo=pegase1.c-s.fr; client-ip=93.17.236.30 X-HE-DKIM-Result: none/none X-HE-Tag: 1617959758-628725 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Le 30/03/2021 =C3=A0 08:07, Aneesh Kumar K.V a =C3=A9crit=C2=A0: > Update _tlbiel_pid() such that we can avoid build errors like below whe= n > using this function in other places. >=20 > arch/powerpc/mm/book3s64/radix_tlb.c: In function =E2=80=98__radix__flu= sh_tlb_range_psize=E2=80=99: > arch/powerpc/mm/book3s64/radix_tlb.c:114:2: warning: =E2=80=98asm=E2=80= =99 operand 3 probably does not match constraints > 114 | asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) > | ^~~ > arch/powerpc/mm/book3s64/radix_tlb.c:114:2: error: impossible constrain= t in =E2=80=98asm=E2=80=99 > make[4]: *** [scripts/Makefile.build:271: arch/powerpc/mm/book3s64/radi= x_tlb.o] Error 1 > m >=20 > With this fix, we can also drop the __always_inline in __radix_flush_tl= b_range_psize > which was added by commit e12d6d7d46a6 ("powerpc/mm/radix: mark __radix= __flush_tlb_range_psize() as __always_inline") >=20 > Signed-off-by: Aneesh Kumar K.V Reviewed-by: Christophe Leroy > --- > arch/powerpc/mm/book3s64/radix_tlb.c | 26 +++++++++++++++++--------- > 1 file changed, 17 insertions(+), 9 deletions(-) >=20 > diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/boo= k3s64/radix_tlb.c > index 409e61210789..817a02ef6032 100644 > --- a/arch/powerpc/mm/book3s64/radix_tlb.c > +++ b/arch/powerpc/mm/book3s64/radix_tlb.c > @@ -291,22 +291,30 @@ static inline void fixup_tlbie_lpid(unsigned long= lpid) > /* > * We use 128 set in radix mode and 256 set in hpt mode. > */ > -static __always_inline void _tlbiel_pid(unsigned long pid, unsigned lo= ng ric) > +static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) > { > int set; > =20 > asm volatile("ptesync": : :"memory"); > =20 > - /* > - * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL= , > - * also flush the entire Page Walk Cache. > - */ > - __tlbiel_pid(pid, 0, ric); > + switch (ric) { > + case RIC_FLUSH_PWC: > =20 > - /* For PWC, only one flush is needed */ > - if (ric =3D=3D RIC_FLUSH_PWC) { > + /* For PWC, only one flush is needed */ > + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); > ppc_after_tlbiel_barrier(); > return; > + case RIC_FLUSH_TLB: > + __tlbiel_pid(pid, 0, RIC_FLUSH_TLB); > + break; > + case RIC_FLUSH_ALL: > + default: > + /* > + * Flush the first set of the TLB, and if > + * we're doing a RIC_FLUSH_ALL, also flush > + * the entire Page Walk Cache. > + */ > + __tlbiel_pid(pid, 0, RIC_FLUSH_ALL); > } > =20 > if (!cpu_has_feature(CPU_FTR_ARCH_31)) { > @@ -1176,7 +1184,7 @@ void radix__tlb_flush(struct mmu_gather *tlb) > } > } > =20 > -static __always_inline void __radix__flush_tlb_range_psize(struct mm_s= truct *mm, > +static void __radix__flush_tlb_range_psize(struct mm_struct *mm, > unsigned long start, unsigned long end, > int psize, bool also_pwc) > { >=20