L2 cache alignment and page coloring

[Jeff Keasler <keasler@llnl.gov>]

Hi,

I work in an HPC environment where we run a process with a tight inner 
loop (entirely contained in the I-cache) to work on large quantities of 
data.  We've reduced system services to minimize our process getting 
swapped out.

I am concerned that using malloc(L2_CACHE_SIZE) in user space is mapping 
the underlying physical pages such that they do not form a cover of the 
L2 cache (i.e. several physical pages are aliasing into the same part of 
the L2 cache).

Are there any tricks available to force a more cache friendly 
virtual-to-physical mapping from user space?

Thanks,
-Jeff

PS  Even better if it is likely to work for L3 cache.

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