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Tue, 13 Oct 2020 18:31:47 +0000 (UTC) IronPort-SDR: rNf7vO8rJDdyZe2frp7UjrU2DYBKunG5COvBoTx4r4HLoxlqY51cY6T/14iurpqwYYwwrD73Ik PhSFZ1av9+wQ== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="183451483" X-IronPort-AV: E=Sophos;i="5.77,371,1596524400"; d="scan'208";a="183451483" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 11:31:46 -0700 IronPort-SDR: N1xn0HQI0ubXW+ZZ5gn2QreU7BQoHP/0atyUS215Vn7NRjG/ItSebl73LdP+GjPjSK62O2AOZS e/mlDqFbQs2A== X-IronPort-AV: E=Sophos;i="5.77,371,1596524400"; d="scan'208";a="346279150" Received: from murawskx-mobl.amr.corp.intel.com (HELO [10.209.9.29]) ([10.209.9.29]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 11:31:45 -0700 Subject: Re: [PATCH RFC V3 4/9] x86/pks: Preserve the PKRS MSR on context switch To: ira.weiny@intel.com, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Andy Lutomirski , Peter Zijlstra Cc: Fenghua Yu , x86@kernel.org, Dave Hansen , Dan Williams , Andrew Morton , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org References: <20201009194258.3207172-1-ira.weiny@intel.com> <20201009194258.3207172-5-ira.weiny@intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201009194258.3207172-5-ira.weiny@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 10/9/20 12:42 PM, ira.weiny@intel.com wrote: > From: Ira Weiny >=20 > The PKRS MSR is defined as a per-logical-processor register. This > isolates memory access by logical CPU. Unfortunately, the MSR is not > managed by XSAVE. Therefore, tasks must save/restore the MSR value on > context switch. >=20 > Define a saved PKRS value in the task struct, as well as a cached > per-logical-processor MSR value which mirrors the MSR value of the > current CPU. Initialize all tasks with the default MSR value. Then, o= n > schedule in, check the saved task MSR vs the per-cpu value. If > different proceed to write the MSR. If not avoid the overhead of the > MSR write and continue. It's probably nice to note how the WRMSR is special here, in addition to the comments below. > #endif /*_ASM_X86_PKEYS_INTERNAL_H */ > diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/pr= ocessor.h > index 97143d87994c..da2381136b2d 100644 > --- a/arch/x86/include/asm/processor.h > +++ b/arch/x86/include/asm/processor.h > @@ -18,6 +18,7 @@ struct vm86; > #include > #include > #include > +#include > #include > #include > #include > @@ -542,6 +543,11 @@ struct thread_struct { > =20 > unsigned int sig_on_uaccess_err:1; > =20 > +#ifdef CONFIG_ARCH_HAS_SUPERVISOR_PKEYS > + /* Saved Protection key register for supervisor mappings */ > + u32 saved_pkrs; > +#endif Could you take a look around thread_struct and see if there are some other MSRs near which you can stash this? This seems like a bit of a lonely place. ... > void flush_thread(void) > { > struct task_struct *tsk =3D current; > @@ -195,6 +212,8 @@ void flush_thread(void) > memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); > =20 > fpu__clear_all(&tsk->thread.fpu); > + > + pks_init_task(tsk); > } > =20 > void disable_TSC(void) > @@ -644,6 +663,8 @@ void __switch_to_xtra(struct task_struct *prev_p, s= truct task_struct *next_p) > =20 > if ((tifp ^ tifn) & _TIF_SLD) > switch_to_sld(tifn); > + > + pks_sched_in(); > } > =20 > /* > diff --git a/arch/x86/mm/pkeys.c b/arch/x86/mm/pkeys.c > index 3cf8f775f36d..30f65dd3d0c5 100644 > --- a/arch/x86/mm/pkeys.c > +++ b/arch/x86/mm/pkeys.c > @@ -229,3 +229,31 @@ u32 update_pkey_val(u32 pk_reg, int pkey, unsigned= int flags) > =20 > return pk_reg; > } > + > +DEFINE_PER_CPU(u32, pkrs_cache); > + > +/** > + * It should also be noted that the underlying WRMSR(MSR_IA32_PKRS) is= not > + * serializing but still maintains ordering properties similar to WRPK= RU. > + * The current SDM section on PKRS needs updating but should be the sa= me as > + * that of WRPKRU. So to quote from the WRPKRU text: > + * > + * WRPKRU will never execute transiently. Memory accesses > + * affected by PKRU register will not execute (even transiently) > + * until all prior executions of WRPKRU have completed execution > + * and updated the PKRU register. > + */ > +void write_pkrs(u32 new_pkrs) > +{ > + u32 *pkrs; > + > + if (!static_cpu_has(X86_FEATURE_PKS)) > + return; > + > + pkrs =3D get_cpu_ptr(&pkrs_cache); > + if (*pkrs !=3D new_pkrs) { > + *pkrs =3D new_pkrs; > + wrmsrl(MSR_IA32_PKRS, new_pkrs); > + } > + put_cpu_ptr(pkrs); > +} >=20 It bugs me a *bit* that this is being called in a preempt-disabled region, but we still bother with the get/put_cpu jazz. Are there other future call-sites for this that aren't in preempt-disabled regions?