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Fri, 16 Jul 2021 01:09:03 -0700 (PDT) Received: from [10.57.33.181] (unknown [10.57.33.181]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 546333F7D8; Fri, 16 Jul 2021 01:09:01 -0700 (PDT) Subject: Re: [RFC 07/10] arm64/mm: Detect and enable FEAT_LPA2 To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: akpm@linux-foundation.org, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, james.morse@arm.com, steven.price@arm.com References: <1626229291-6569-1-git-send-email-anshuman.khandual@arm.com> <1626229291-6569-8-git-send-email-anshuman.khandual@arm.com> <18c42dd0-b6db-d118-dad0-cac0bf6ab2ce@arm.com> <8adefac5-c677-1fca-20dd-bba8543f8d59@arm.com> From: Suzuki K Poulose Message-ID: <429105f9-e967-492e-1d1f-5bb913ef6854@arm.com> Date: Fri, 16 Jul 2021 09:08:57 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <8adefac5-c677-1fca-20dd-bba8543f8d59@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Authentication-Results: imf05.hostedemail.com; dkim=none; dmarc=pass (policy=none) header.from=arm.com; spf=pass (imf05.hostedemail.com: domain of suzuki.poulose@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=suzuki.poulose@arm.com X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 240405013C6F X-Stat-Signature: ksiku63wg1fegkaqsqwigfdw8rmgg83z X-HE-Tag: 1626422944-791410 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 16/07/2021 08:06, Anshuman Khandual wrote: >=20 > On 7/14/21 1:51 PM, Suzuki K Poulose wrote: >> On 14/07/2021 03:21, Anshuman Khandual wrote: >>> Detect FEAT_LPA2 implementation early enough during boot when request= ed via >>> CONFIG_ARM64_PA_BITS_52_LPA2 and remember in a variable arm64_lpa2_en= abled. >>> This variable could then be used to turn on TCR_EL1.TCR_DS effecting = the 52 >>> bits PA range or fall back to default 48 bits PA range if FEAT_LPA2 f= eature >>> was requested but found not to be implemented. >>> >>> Signed-off-by: Anshuman Khandual >>> --- >>> =C2=A0 arch/arm64/include/asm/memory.h |=C2=A0 1 + >>> =C2=A0 arch/arm64/kernel/head.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 | 15 +++++++++++++++ >>> =C2=A0 arch/arm64/mm/mmu.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 3 +++ >>> =C2=A0 arch/arm64/mm/proc.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 9 +++++++++ >>> =C2=A0 4 files changed, 28 insertions(+) >>> >>> diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm= /memory.h >>> index 824a365..d0ca002 100644 >>> --- a/arch/arm64/include/asm/memory.h >>> +++ b/arch/arm64/include/asm/memory.h >>> @@ -178,6 +178,7 @@ >>> =C2=A0 #include >>> =C2=A0 =C2=A0 extern u64=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 vabits_actual; >>> +extern u64=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 arm64_lpa2_enabled; >>> =C2=A0 =C2=A0 extern s64=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 memstart_addr; >>> =C2=A0 /* PHYS_OFFSET - the physical address of the start of memory.= */ >>> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S >>> index 6444147..9cf79ea 100644 >>> --- a/arch/arm64/kernel/head.S >>> +++ b/arch/arm64/kernel/head.S >>> @@ -94,6 +94,21 @@ SYM_CODE_START(primary_entry) >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 adrp=C2=A0=C2=A0=C2=A0 x23, __PHYS_OF= FSET >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 and=C2=A0=C2=A0=C2=A0 x23, x23, MIN_K= IMG_ALIGN - 1=C2=A0=C2=A0=C2=A0 // KASLR offset, defaults to 0 >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bl=C2=A0=C2=A0=C2=A0 set_cpu_boot_mod= e_flag >>> + >>> +#ifdef CONFIG_ARM64_PA_BITS_52_LPA2 >>> +=C2=A0=C2=A0=C2=A0 mrs=C2=A0=C2=A0=C2=A0=C2=A0 x10, ID_AA64MMFR0_EL1 >>> +=C2=A0=C2=A0=C2=A0 ubfx=C2=A0=C2=A0=C2=A0 x10, x10, #ID_AA64MMFR0_TG= RAN_SHIFT, 4 >>> +=C2=A0=C2=A0=C2=A0 cmp=C2=A0=C2=A0=C2=A0=C2=A0 x10, #ID_AA64MMFR0_TG= RAN_LPA2 >>> +=C2=A0=C2=A0=C2=A0 b.ne=C2=A0=C2=A0=C2=A0 1f >> >> For the sake of forward compatibility, this should be "b.lt" > Right, I guess we could assume that the feature will be present from th= e > current ID_AA64MMFR0_TGRAN_LPA2 values onward in the future. But should > not this also be capped at ID_AA64MMFR0_TGRAN_SUPPORTED_MAX as the uppe= r > limit is different for 4K and 16K page sizes. Absolutely. Cheers Suzuki >=20