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Thu, 09 Jan 2025 15:00:14 -0800 (PST) Received: from [192.168.86.29] ([83.105.36.37]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4b8180sm2902142f8f.76.2025.01.09.15.00.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jan 2025 15:00:14 -0800 (PST) Message-ID: <3ecfa4ff-9916-4ac1-8464-c1b6615b832a@citrix.com> Date: Thu, 9 Jan 2025 23:00:12 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 00/12] AMD broadcast TLB invalidation To: Yosry Ahmed Cc: akpm@linux-foundation.org, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jackmanb@google.com, kernel-team@meta.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, luto@kernel.org, mingo@redhat.com, nadav.amit@gmail.com, peterz@infradead.org, reijiw@google.com, riel@surriel.com, tglx@linutronix.de, x86@kernel.org, zhengqi.arch@bytedance.com References: Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam05 X-Stat-Signature: u4x6j5rs7reewoc9mm9biiq7uj6cd7j7 X-Rspamd-Queue-Id: 21181C0010 X-Rspam-User: X-HE-Tag: 1736463615-115181 X-HE-Meta: U2FsdGVkX1/Oy4J4EUIxj5Z2yUqW6v70jxNJcunP0+xUkrLRsuWwraovf6exsAYZEr2e8gIzTEk4GcKBQLGhdCyrNTEoloG85TRmYxen2q/YJrMcpNQu/mQUnDR5Y1vyo9jLpMuuR2Y4wQYG2u57Y7Gg+h/LlVRcK0k6UHAFyic1qCSfbgYks4aXaewL0gwi2fvIl0EzC4YV29zVmSRxXh5GeA35L8MlLdQwKcEt5IEVW7712E0iPHlNdL97I0OnHqK1pNdSQIHKTkvnYhVAVc3VRSHDAQkXzajBenOeeOFfCg2xIj+Rl5K8JjnQGkBdp48rrCSdbG0F/1nFa2m9HZLzOWlmKqkb/8/D5lhTJK2EZAU8vRzN3julNf59bK5Kq5HRGFtBwDxvXGzLI6pROpcr1xmpuNkL/7LW0h1RpV8Ltac17qXk+JCboFklO7ROoAmubPo/CyD+IQA9doJ6d8wPe71Jjmao+T7KJg15DN6ANXSr5sZfbyhqjgrEDkzuIztFUDtaRHt/Dgj9hcvmAimZBH3+JassQFUqndwzeJYbc2z+YRqjrzXe7/v9KDaYW7WddtTkV1FVO8ym+sxbZ3r9D2UyZu6uvqYEFWvzfuQK43wT/ZU6lhbLnHiXGJr4H1yM49UdAD7Kfn5lwEi7KAJkKK8uGZ3amTmu1kN8Rj7aQXPLOagOvy/7n3aHL5EgATjm4kTVSumbgkwgQ9raq/L4cLZ0dH79N1ciA0P3rJ+THQv8k2bdrNFgeCo9FUMT079lmYHrdn2b8cGrszpN2vjNkZhByMC1gCGTIsbOfOLVa5IwZ6a+kCmTqtI0dejj/c3EUpv11sX273xjGhiGhCfgGZE0SaQBEZpZ6x6A4TfcPNimPK29oFfomskAzOX7nmP3ejCGcgHUoTzThOILz1uXUwWtFmKK57p/m9bU6gDYgGUvMd7O9XWgKsR0kH+yzCM41ck1bQOWp3DXnRb MYyKOI5N OSNso0LrWu4BGwG0zrX4aHQdogtjidmjAWlbRlI2MdnCHumLppp4cG3ASRHAz8IQ6GR8rs1lH9CtSdHaQxbqGWT0aCMZy3/pFEZXcXxxWiAAltAPQjYzR0+Mmhfer6IGtoc77IpPABLEE68SYfdn0fX3eGn6MVK2Llf4JA5HmtW9aSwj8cAOzv6ZH5wneJ7ouUO7b0cELHge3FDvhsc0pKqVuv98x0ppw0OL0ayHFDzTGQXC85f9twbOQLP20wdj5qhhcfG9c4Y9O8iVT+4jEVTCo01H+1vSnU5oEupadvltJaFALfzz1L8Z9CON4foVzFxj8MZMOsf21oLxY9pWlNPoDQH5G9YjPJVUkrbgRlvaGnrJEt9Yke5bJNeIJ4ZubBPRw7B53t3dKnd/getJmG312AGHy7dK0sGsfsdK9gLYpINrb1VeQKIuFqR0u4vhJYvIotx03KCI8FHmgfOIbOVBPsuUohj0dIQvB4apFReha88cerWQNM11lbTW4o1u0Z50vxauaum4Obb/8/9oYy3+jmLHkVgVfEadrttLrrOt+ZsOztZYCrXlvRUFojc+5ZFODKN1K5yq6NNh1EIXgBZBm8gOJSkH1VceV X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On 09/01/2025 9:32 pm, Yosry Ahmed wrote: > On Wed, Jan 8, 2025 at 6:47 PM Andrew Cooper wrote: >>>> I suspect AMD wouldn't tell us exactly ;) >>> Well, ideally they would just tell us the conditions under which CPUs >>> respond to the broadcast TLB flush or the expectations around latency. >> [Resend, complete this time] >> >> Disclaimer. I'm not at AMD; I don't know how they implement it; I'm >> just a random person on the internet. But, here are a few things that >> might be relevant to know. >> >> AMD's SEV-SNP whitepaper [1] states that RMP permissions "are cached in >> the CPU TLB and related structures" and also "When required, hardware >> automatically performs TLB invalidations to ensure that all processors >> in the system see the updated RMP entry information." >> >> That sentence doesn't use "broadcast" or "remote", but "all processors" >> is a pretty clear clue. Broadcast TLB invalidations are a building >> block of all the RMP-manipulation instructions. >> >> Furthermore, to be useful in this context, they need to be ordered with >> memory. Specifically, a new pagewalk mustn't start after an >> invalidation, yet observe the stale RMP entry. >> >> >> x86 CPUs do have reasonable forward-progress guarantees, but in order to >> achieve forward progress, they need to e.g. guarantee that one memory >> access doesn't displace the TLB entry backing a different memory access >> from the same instruction, or you could livelock while trying to >> complete a single instruction. >> >> A consequence is that you can't safely invalidate a TLB entry of an >> in-progress instruction (although this means only the oldest instruction >> in the pipeline, because everything else is speculative and potentially >> transient). >> >> >> INVLPGB invalidations are interrupt-like from the point of view of the >> remote core, but are microarchitectural and can be taken irrespective of >> the architectural Interrupt and Global Interrupt Flags. As a >> consequence, they'll need wait until an instruction boundary to be >> processed. While not AMD, the Intel RAR whitepaper [2] discusses the >> handling of RARs on the remote processor, and they share a number of >> constraints in common with INVLPGB. >> >> >> Overall, I'd expect the INVLPGB instructions to be pretty quick in and >> of themselves; interestingly, they're not identified as architecturally >> serialising. The broadcast is probably posted, and will be dealt with >> by remote processors on the subsequent instruction boundary. TLBSYNC is >> the barrier to wait until the invalidations have been processed, and >> this will block for an unspecified length of time, probably bounded by >> the "longest" instruction in progress on a remote CPU. e.g. I expect it >> probably will suck if you have to wait for a WBINVD instruction to >> complete on a remote CPU. >> >> That said, architectural IPIs have the same conditions too, except on >> top of that you've got to run a whole interrupt handler. So, with >> reasonable confidence, however slow TLBSYNC might be in the worst case, >> it's got absolutely nothing on the overhead of doing invalidations the >> old fashioned way. > Generally speaking, I am not arguing that TLB flush IPIs are worse > than INLPGB/TLBSYNC, I think we should expect the latter to perform > better in most cases. > > But there is a difference here because the processor executing TLBSYNC > cannot serve interrupts or NMIs while waiting for remote CPUs, because > they have to be served at an instruction boundary, right? That's as per the architecture, yes.  NMIs do have to be served on instruction boundaries.  An NMI that becomes pending while a TLBSYNC is in progress will have to wait until the TLBSYNC completes. (Probably.  REP string instructions and AVX scatter/gather have explicit behaviours that them them be interrupted, and to continue from where they left off when the interrupt handler returns.  Depending on how TLBSYNC is implemented, it's just possible it has this property too.) > Unless > TLBSYNC is an exception to that rule, or its execution is considered > completed before remote CPUs respond (i.e. the CPU executes it quickly > then enters into a wait doing "nothing"). > > There are also intriguing corner cases that are not documented. For > example, you mention that it's reasonable to expect that a remote CPU > does not serve TLBSYNC except at the instruction boundary. INVLPGB needs to wait for an instruction boundary in order to be processed. All TLBSYNC needs to do is wait until it's certain that all the prior INVLPGBs issued by this CPU have been serviced. > What if > that CPU is executing TLBSYNC? Do we have to wait for its execution to > complete? Is it possible to end up in a deadlock? This goes back to my > previous point about whether TLBSYNC is a special case or when it's > considered to have finished executing. Remember that the SEV-SNP instruction (PSMASH, PVALIDATE, RMP{ADJUST,UPDATE,QUERY,READ}) have an INVLPGB/TLBSYNC pair under the hood.  You can execute these instructions on different CPUs in parallel. It's certainly possible AMD missed something and there's and there's a deadlock case in there.  But Google do offer SEV-SNP VMs and have the data and scale to know whether such a deadlock is happening in practice. > > I am sure people thought about that and I am probably worried over > nothing, but there's little details here so one has to speculate. > > Again, sorry if I am making a fuss over nothing and it's all in my head. It's absolutely a valid question to ask. But x86 is full of longer delays than this.  The GIF for example can block NMIs until the hypervisor is complete with the world switch, and it's left as an exercise to software not to abuse this.  Taking an SMI will be orders of magnitude more expensive than anything discussed here. ~Andrew