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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id f2-20020a170902ce8200b00176acd80f69sm1540295plg.102.2022.11.03.21.33.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Nov 2022 21:33:42 -0700 (PDT) Message-ID: <3d8aa022-a73e-aa27-5219-12dcf9f20443@rivosinc.com> Date: Thu, 3 Nov 2022 21:33:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features. Content-Language: en-US To: Chris Stillson Cc: Greentime Hu , Guo Ren , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Eric Biederman , Kees Cook , Anup Patel , Atish Patra , Oleg Nesterov , Guo Ren , Heinrich Schuchardt , Arnaud Pouliquen , Paolo Bonzini , Arnd Bergmann , Heiko Stuebner , Jisheng Zhang , Dao Lu , Sunil V L , Andy Chiu , Guo Ren , lkml , linux-riscv , linux-mm@kvack.org References: <20220921214439.1491510-1-stillson@rivosinc.com> <20220921214439.1491510-5-stillson@rivosinc.com> From: Vineet Gupta In-Reply-To: <20220921214439.1491510-5-stillson@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit ARC-Authentication-Results: i=1; imf06.hostedemail.com; dkim=pass header.d=rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=hYEu2TPY; spf=pass (imf06.hostedemail.com: domain of vineetg@rivosinc.com designates 209.85.215.174 as permitted sender) smtp.mailfrom=vineetg@rivosinc.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1667536424; a=rsa-sha256; cv=none; b=ahS1ZrLH8M1MlfuuUUDVQqvBWrGJz/8COz/cqh1DW9wcsoDiPovwGaGk6ofzhNf1S2hcgD AdtRylARp+9sO/LBB+OTTxb+xcHRszr1V3S1CHNVKA9T9KjI6a21SP7UVRjHXUNWqTNiSj fKtY2J8u30M8ykjNhE1QqM5UodK+uLM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1667536424; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=wepWE4KrXFxsKEWcFpjgx18r9i0Jh/wR/FjXQiA0858=; b=L/KrIF9f77mDvD7fTPyzqjqMMZwmvr1j9V9HcSM0RCzLFJOUvJX2MqCIIOSqw8WEdWmwSV DUFU6U6IP8W7Rg96+LqK9aqygpjLbY1XOsg6T1roWFHCXTZUSBrxkY/NA9AtoG1vcL7Wvs iQuVLwiFdfC0nrJjHM3cevd7uSoflyE= X-Stat-Signature: 1o48mriijr1yuacmz3yrid6aoejqzh4g X-Rspamd-Queue-Id: 6EB86180002 Authentication-Results: imf06.hostedemail.com; dkim=pass header.d=rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=hYEu2TPY; spf=pass (imf06.hostedemail.com: domain of vineetg@rivosinc.com designates 209.85.215.174 as permitted sender) smtp.mailfrom=vineetg@rivosinc.com; dmarc=none X-Rspam-User: X-Rspamd-Server: rspam12 X-HE-Tag: 1667536424-651148 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 9/21/22 14:43, Chris Stillson wrote: > From: Greentime Hu > > This patch is used to detect vector support status of CPU and use > riscv_vsize to save the size of all the vector registers. It assumes > all harts has the same capabilities in SMP system. Patch title is horrible. The meat of patch is vector state save/restore, but no users of it yet. And then there are random unrelated snippets thrown in same patch. > +#ifdef CONFIG_FPU > +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > +#endif This needs to be broken out to a FPU patch which actually uses cpu_hwcap_fpu. > +#ifdef CONFIG_VECTOR > +#include > +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector); > +unsigned long riscv_vsize __read_mostly; > +#endif I'd move this patch v2/17 as part of detection etc. > +#ifdef CONFIG_VECTOR > + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { > + static_branch_enable(&cpu_hwcap_vector); Ditto. > + /* There are 32 vector registers with vlenb length. */ > + rvv_enable(); > + riscv_vsize = csr_read(CSR_VLENB) * 32; Ditto. > + rvv_disable(); But guess these needs to be added first as well, see below. > +#ifdef CONFIG_VECTOR > +#include > +EXPORT_SYMBOL(rvv_enable); > +EXPORT_SYMBOL(rvv_disable); As suggested in prior review comment, we don't need to EXPORT these, for now at least. > diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S > new file mode 100644 > index 000000000000..9f7dc70c4443 > --- /dev/null > +++ b/arch/riscv/kernel/vector.S > @@ -0,0 +1,93 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2012 Regents of the University of California > + * Copyright (C) 2017 SiFive > + * Copyright (C) 2019 Alibaba Group Holding Limited > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation, version 2. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ SPDX hdr ... > + > +#include > + > +#include > +#include > +#include > + > +#define vstatep a0 > +#define datap a1 > +#define x_vstart t0 > +#define x_vtype t1 > +#define x_vl t2 > +#define x_vcsr t3 > +#define incr t4 > +#define status t5 > + A few words here as to when is this save/restore done. Perhaps best to add this code in the patch which actually uses these. > +ENTRY(__vstate_save) > + li status, SR_VS > + csrs CSR_STATUS, status > + > + csrr x_vstart, CSR_VSTART > + csrr x_vtype, CSR_VTYPE > + csrr x_vl, CSR_VL > + csrr x_vcsr, CSR_VCSR > + vsetvli incr, x0, e8, m8, ta, ma > + vse8.v v0, (datap) > + add datap, datap, incr > + vse8.v v8, (datap) > + add datap, datap, incr > + vse8.v v16, (datap) > + add datap, datap, incr > + vse8.v v24, (datap) > + > + REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep) > + REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep) > + REG_S x_vl, RISCV_V_STATE_VL(vstatep) > + REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep) > + > + csrc CSR_STATUS, status > + ret > +ENDPROC(__vstate_save) > + > +ENTRY(__vstate_restore) > + li status, SR_VS > + csrs CSR_STATUS, status This is rvv_enable code duplicated inline. > + > + vsetvli incr, x0, e8, m8, ta, ma > + vle8.v v0, (datap) > + add datap, datap, incr > + vle8.v v8, (datap) > + add datap, datap, incr > + vle8.v v16, (datap) > + add datap, datap, incr > + vle8.v v24, (datap) > + > + REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep) > + REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep) > + REG_L x_vl, RISCV_V_STATE_VL(vstatep) > + REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep) > + vsetvl x0, x_vl, x_vtype > + csrw CSR_VSTART, x_vstart > + csrw CSR_VCSR, x_vcsr > + > + csrc CSR_STATUS, status > + ret > +ENDPROC(__vstate_restore) > + > +ENTRY(rvv_enable) > + li status, SR_VS > + csrs CSR_STATUS, status > + ret > +ENDPROC(rvv_enable) > + > +ENTRY(rvv_disable) > + li status, SR_VS > + csrc CSR_STATUS, status > + ret > +ENDPROC(rvv_disable) I'd suggest these be made asm macros, to avoid function call overhead and duplication as in save/restore above.